JPS58199533A - 半導体装置 - Google Patents

半導体装置

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Publication number
JPS58199533A
JPS58199533A JP57081448A JP8144882A JPS58199533A JP S58199533 A JPS58199533 A JP S58199533A JP 57081448 A JP57081448 A JP 57081448A JP 8144882 A JP8144882 A JP 8144882A JP S58199533 A JPS58199533 A JP S58199533A
Authority
JP
Japan
Prior art keywords
layer
insulating film
wirings
aluminum
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57081448A
Other languages
English (en)
Inventor
Kenji Yoshinaga
吉永　賢爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57081448A priority Critical patent/JPS58199533A/ja
Publication of JPS58199533A publication Critical patent/JPS58199533A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明はＭｏ　（モリブデン）ゲート系ＭＯ８ＦＥＴ（
金属酸化物半導体電界効果トランジスタ）の電極構造に
関する。
ＭｏゲートＭＯ８ＦＥＴのＭｏゲート電極−配線構造に
おいては、第１図、第２図に示すように、Ｓｉ（シリコ
ン）基板１上にうすい絶縁膜＜５ｉＯＸ膜）２を介して
設けた絶縁ゲート電極のＭＯ層３の一部を絶縁膜（Ｓｊ
０２膜）４上に延長し、第２の絶縁膜（ＰＳＧ等）５の
スルーホール６を通してＡ１（アルミニウム）層からな
る配線７を接触させ、このＡ！配線７の延長部に広い面
積の配線端子８を形成しこれをポンディングパッドとし
てＡｕ（金）ワイヤ９の先端ホールを熱圧着等の手段で
ボンディングしている。
Ｍｏゲート電極−Ａ１配線構造では、ゲート抵抗はＭＯ
とＡ−ｅとの接触部分がポンディングパッドから離れた
位置にあるためＭｏ　−Ａ、ｅ接触抵抗によって左右さ
れるっこのＭｏ　−Ａ、ａの接触部分においては、ＭＯ
層上にＡ、、ｅ蒸着直後は接触抵抗は小さいが、Ａ、ｅ
固定のための通常の熱処理をするとＭｏ−Ａｊ？界面の
０２が障壁となって抵抗値が太き（なる。このようにゲ
ート抵抗が太錠（なるとＭ　ＯＳ　Ｆ　Ｅ’Ｉ’におけ
る高尚波％性がわるくなり、電力利得、雑音等の点で問
題があった。
本発明は上記した問題を解決するためのもので、その目
的は、ＭｏゲートＭＯ８ＦＥ’ｌ’におけロＭＯ−Ａ、
＃接触抵抗を低減し、高周波％性を改善することにある
。
ＪＲ下木本発明一つの実施例にそっ℃詳述する。
第３図、第４図において、１は８１基板、２はうすいゲ
ート絶縁膜（Ｓｉｆｔ膜）でこの土にＭ。
層３を形成し、その一部をＭＯ配線として厚い絶縁膜４
上に延長し、その配線端子を広（形成する。　□この上
に第２の絶縁膜（リン・シリケートガラス等）５の大径
のスルーホール６を通してＭ層８を接触させ、ポンディ
ングパッドとしてＡｕワイヤ９をボンディングする。こ
のＡｕワイヤのボンディングにより、Ａ−ｅ層を通して
ＡｕとＭｏが近接又は接触し接触抵抗を下げることにな
る。
以上実施例で述べた本発明によれば下記の自由で前記目
的を達成できる。
（ｌｌＭｏ　−ＡＪＩ接触部は在来のスルーホールが３
０μｍ×３０μｍ程度であるのに対し、本発明ではポン
ディングパッド下にスルーホールを設けるために１００
μｍ　Ｘ　１００μｍと面積で約１０倍相度も大きくな
れば接触抵抗は１０分の１となる。
（２１Ｍｏ　−Ａ−ｅ接触部はポンディングパッドの面
下に設けられるため、Ａｕワイ□ヤをＵ層に熱圧着によ
りボンディングするとき、Ａｕの一部はＭを通し、ある
いはＭを突き抜けてＭｏ層に近接ないし接触し、単位面
積における接触抵抗を小さぐすることができる。
（３１Ｍｏ層による配線は在米のものより長くなるがＭ
Ｏ層自体のバルク抵抗はＭｏ−Ａ４接触抵抗よりも小さ
いから全体としてＭｏ層の延、長、によるゲート抵抗へ
の影響は小さい。
（４）本発明によるＭｏ−Ａ−ｅ構造をＮるには配線パ
ターンを変えるだけでプロセスに変更はなく、又、ＭＯ
８ＦＥＴ全体の面積も特に増加しない。
以上によりＭｏ−Ａ−ｅ接触抵抗を低減することで、高
周波特性が著しく改善され、電力利得を例えば５〜１０
ｄＢ（Ｒｏ太Ｌ　１ト２０ｄＢ（Ｒｏ小）に改善し、又
、ノイズを５〜６ｄ８から３〜４ｄ、に改善することが
可能となった。
本発明はＭｏ　−Ａ−ｅ未配線を有する半導体装置、特
ＫＭｏゲート系ＭＯ８ＦＥＴＫ適用するものである。
【図面の簡単な説明】
第１図は在来のＭｏグー）ＭＯＳＦＥＴの要部平面図、 第２図は第１図におけるＡ−Ａ’断面図、第３図は本発
明によるＭｏグー）ＭＯＳＦＥＴの要部平面図、 第４図は第３図におけるＡ−Ｘ断面図である。 １・・・Ｓ＋基板、２・・・うすい絶縁膜、３・・・Ｍ
ｏ層、４・・・厚い絶縁膜、５・・・第２の絶縁膜、６
・・・スルーホール、７・・匂す層、８・・・ポンディ
ングパッド、９・・・Ａｕワイヤ。 第　　１　　図 第　　２　　図　　　　　　　。

Claims (1)

    【特許請求の範囲】
  1. １、電極の一部にモリブデン層を有し、このモリブデン
    層にアルミニウム層を接触してそのアルミニウム層の延
    長部を配線端子とした半導体装置において、モリブデン
    層とアルミニウム層の接触部を配線端子の直下に形成し
    たことを特徴とする半導体装置。
JP57081448A 1982-05-17 1982-05-17 半導体装置 Pending JPS58199533A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57081448A JPS58199533A (ja) 1982-05-17 1982-05-17 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57081448A JPS58199533A (ja) 1982-05-17 1982-05-17 半導体装置

Publications (1)

Publication Number Publication Date
JPS58199533A true JPS58199533A (ja) 1983-11-19

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Family Applications (1)

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JP57081448A Pending JPS58199533A (ja) 1982-05-17 1982-05-17 半導体装置

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4993622A (en) * 1987-04-28 1991-02-19 Texas Instruments Incorporated Semiconductor integrated circuit chip interconnections and methods
EP0646959A1 (en) * 1993-09-30 1995-04-05 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Metallization and bonding process for manufacturing power semiconductor devices
US5719448A (en) * 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4993622A (en) * 1987-04-28 1991-02-19 Texas Instruments Incorporated Semiconductor integrated circuit chip interconnections and methods
US5719448A (en) * 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
EP0646959A1 (en) * 1993-09-30 1995-04-05 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Metallization and bonding process for manufacturing power semiconductor devices
US5773899A (en) * 1993-09-30 1998-06-30 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Bonding pad for a semiconductor chip
US5869357A (en) * 1993-09-30 1999-02-09 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Metallization and wire bonding process for manufacturing power semiconductor devices

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