JPS57206069A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS57206069A
JPS57206069A JP57077786A JP7778682A JPS57206069A JP S57206069 A JPS57206069 A JP S57206069A JP 57077786 A JP57077786 A JP 57077786A JP 7778682 A JP7778682 A JP 7778682A JP S57206069 A JPS57206069 A JP S57206069A
Authority
JP
Japan
Prior art keywords
region
channel
inversion layer
layer region
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57077786A
Other languages
Japanese (ja)
Inventor
Tadashi Kuragami
Yoshiharu Fujimoto
Taiichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57077786A priority Critical patent/JPS57206069A/en
Publication of JPS57206069A publication Critical patent/JPS57206069A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

PURPOSE:To form the memory cell with large capacity in small space by a method wherein the depletion type inversion layer region is provided on the substrate surface to be one electrode of the capacity element bringing the channel inversion layer region into direct contact with the channel region. CONSTITUTION:In the memory cell comprising one transistor element and one capacity element, the drain diffused region 22 of MOSFET Q1 is formed connecting to the digit line 21 and the depletion type inversion region 25 to be one electrode of the capacity element C1 is also formed. Next the channel region 23 is formed between said regions 22 and 25 while the gate connecting to the address line 26 is provided on the channel region 23. When the inversion layer region 25 also serves as the source region of MOSFET Q1 and the specified potential is impressed on the address line 26 to form the channel 23, the drain region 22 and the inversion layer region 25 are made conductive.
JP57077786A 1982-05-10 1982-05-10 Semiconductor memory device Pending JPS57206069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57077786A JPS57206069A (en) 1982-05-10 1982-05-10 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57077786A JPS57206069A (en) 1982-05-10 1982-05-10 Semiconductor memory device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP50071756A Division JPS51147226A (en) 1975-06-13 1975-06-13 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS57206069A true JPS57206069A (en) 1982-12-17

Family

ID=13643649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57077786A Pending JPS57206069A (en) 1982-05-10 1982-05-10 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS57206069A (en)

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