JPS57162464A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS57162464A JPS57162464A JP4744181A JP4744181A JPS57162464A JP S57162464 A JPS57162464 A JP S57162464A JP 4744181 A JP4744181 A JP 4744181A JP 4744181 A JP4744181 A JP 4744181A JP S57162464 A JPS57162464 A JP S57162464A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- channel
- diffusion
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 108091006146 Channels Proteins 0.000 abstract 6
- 238000009792 diffusion process Methods 0.000 abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To reduce the lateral directional resistance component of a channel layer, and to suppress parasitic bipolar transistor operation of a semiconductor device by a method wherein a buried layer of reverse conductive type high impurity concentration is provided in a semiconductor substrate, and the nighborhood of the channel part of a channel layer and the channel contact region are connected through the buried layer. CONSTITUTION:The P type buried layer 22 is formed by diffusion in the N type Si substrat 21, an N type layer 21' is made to grow epitaxially on the whole surface containing the buried layer, the P<+> type channel contact region 4 is formed by diffusion extending from the surface of the layer thereof to the end part of the layer 22 making the bottom part to stop in the layer 22, and the region 4 and the layer 22 are connected in the inside of the substrate 21. Then the unnecessitating part of an SiO2 film7 generated at this time is removed, a gate oxide film 5 and a polycrystalline Si layer 6 are pilled up being laminated, an opening 23 is formed corresponding to the layer 22, the P type channel layer 2 to enter into the layer 22 is formed by diffusion, and the channel layer is bridged to the region 4. After then, an N type source region 3 is formed by diffusion in the layer 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4744181A JPS57162464A (en) | 1981-03-31 | 1981-03-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4744181A JPS57162464A (en) | 1981-03-31 | 1981-03-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57162464A true JPS57162464A (en) | 1982-10-06 |
Family
ID=12775225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4744181A Pending JPS57162464A (en) | 1981-03-31 | 1981-03-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57162464A (en) |
-
1981
- 1981-03-31 JP JP4744181A patent/JPS57162464A/en active Pending
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