JPS5698872A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5698872A
JPS5698872A JP42180A JP42180A JPS5698872A JP S5698872 A JPS5698872 A JP S5698872A JP 42180 A JP42180 A JP 42180A JP 42180 A JP42180 A JP 42180A JP S5698872 A JPS5698872 A JP S5698872A
Authority
JP
Japan
Prior art keywords
layer
type
source
platinum
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP42180A
Other languages
Japanese (ja)
Other versions
JPS6243551B2 (en
Inventor
Hiroki Muta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP42180A priority Critical patent/JPS5698872A/en
Publication of JPS5698872A publication Critical patent/JPS5698872A/en
Publication of JPS6243551B2 publication Critical patent/JPS6243551B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To simplify the preparation process of the ICs, by making the gate, source and drain electrodes with the use of platinum silicides made in the presence of polyscrystal or amorphous Si and by making the wires that extend from the said electrodes by the same process on the same layer. CONSTITUTION:On the P<+> type Si substrate 31, the device separation layer 32, the P<+> type region 33 as the channel stopper and the N<+> type layers 34a, 34b and 34c which correspond to the source and drain regions are formed, and the N type layer 35 is further formed as the active layer. Next, the part where the gate electrode 36a and 36b of Schottky junction borders on the layer 35 and the part where the ohmic electrode 36c, 36d, 36b of the source and drain regions borders on the layer 34b are formed. All these are made of platinum silicides. The wires that extend from each of these electrodes into the regions 37 are made of the platinum layer 38 by the same process. These platinum silicides are made of the polycrystal or amorphous Si as the starting material.
JP42180A 1980-01-07 1980-01-07 Preparation of semiconductor device Granted JPS5698872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP42180A JPS5698872A (en) 1980-01-07 1980-01-07 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP42180A JPS5698872A (en) 1980-01-07 1980-01-07 Preparation of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5698872A true JPS5698872A (en) 1981-08-08
JPS6243551B2 JPS6243551B2 (en) 1987-09-14

Family

ID=11473332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP42180A Granted JPS5698872A (en) 1980-01-07 1980-01-07 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5698872A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178642A (en) * 1984-02-24 1985-09-12 Fujitsu Ltd Manufacture of semiconductor device
JPH08227901A (en) * 1995-02-20 1996-09-03 Nec Corp Fabrication of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60178642A (en) * 1984-02-24 1985-09-12 Fujitsu Ltd Manufacture of semiconductor device
JPH0530055B2 (en) * 1984-02-24 1993-05-07 Fujitsu Ltd
JPH08227901A (en) * 1995-02-20 1996-09-03 Nec Corp Fabrication of semiconductor device
JP2687917B2 (en) * 1995-02-20 1997-12-08 日本電気株式会社 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS6243551B2 (en) 1987-09-14

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