JPH0530055B2 - - Google Patents

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Publication number
JPH0530055B2
JPH0530055B2 JP59033528A JP3352884A JPH0530055B2 JP H0530055 B2 JPH0530055 B2 JP H0530055B2 JP 59033528 A JP59033528 A JP 59033528A JP 3352884 A JP3352884 A JP 3352884A JP H0530055 B2 JPH0530055 B2 JP H0530055B2
Authority
JP
Japan
Prior art keywords
layer
silicide
silicon
melting point
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59033528A
Other languages
Japanese (ja)
Other versions
JPS60178642A (en
Inventor
Yoshimi Shiotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3352884A priority Critical patent/JPS60178642A/en
Publication of JPS60178642A publication Critical patent/JPS60178642A/en
Publication of JPH0530055B2 publication Critical patent/JPH0530055B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置等の配線層に用いる高融点
金属シリサイド層の形成に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the formation of a high melting point metal silicide layer used for wiring layers of semiconductor devices and the like.

(b) 技術の背景 集積回路の高集積化に伴い、最上層の配線材料
としてはアルミニウム、中間層の配線材料として
は2〜3層構造のドープした多結晶珪素層が多用
されている。特にMIS素子のゲートには多結晶珪
素層を用いるため、ゲートに接続されるメモリ素
子のワード線多結晶珪素層を極めて広く使用して
いる。
(b) Background of the Technology As integrated circuits become more highly integrated, aluminum is often used as the wiring material for the top layer, and doped polycrystalline silicon layers with a two to three layer structure are used as the wiring material for the intermediate layer. In particular, since a polycrystalline silicon layer is used for the gate of the MIS element, the word line polycrystalline silicon layer of the memory element connected to the gate is extremely widely used.

しかし集積回路の高速化に伴い、多結晶珪素層
の抵抗が金属より大きいため、配線抵抗と容量の
積による遅延が問題になる。このため配線材料と
して高融点金属が検討されたが、 イオン注入のマスクにならない。
However, as integrated circuits become faster, the resistance of polycrystalline silicon layers is greater than that of metals, so delays due to the product of wiring resistance and capacitance become a problem. For this reason, high-melting point metals were considered as wiring materials, but they cannot be used as masks for ion implantation.

酸化しやすい。 Easy to oxidize.

耐薬品性が悪い。 Poor chemical resistance.

接触抵抗が大きい。 Contact resistance is large.

等の欠点を有する。It has the following disadvantages.

そのため高融点金属シリサイドが用いられるよ
うになつた。例えばタングステン・シリサイド、
モリブデン・シリサイド、チタン・シリサイド、
タンタル・シリサイド等が用いられる。これらの
シリサイドの比抵抗は10〜100μΩcmで、多結晶珪
素の最低値1000μΩcmより1〜2桁小さく、さら
に珪素に対するオーム性接合が形成され易い。比
抵抗は例えばタングステン・シリサイド30〜
100μΩcm、モリブデン・シリサイド40〜100μΩ
cm、タンタル・シリサイドは30〜60μΩcm、チタ
ン・シリサイドは13〜30μΩcmである。
Therefore, high melting point metal silicides have come to be used. For example, tungsten silicide,
Molybdenum silicide, titanium silicide,
Tantalum silicide etc. are used. The specific resistance of these silicides is 10 to 100 .mu..OMEGA.cm, which is one to two digits smaller than the lowest value of polycrystalline silicon, 1000 .mu..OMEGA.cm, and furthermore, ohmic junctions with silicon are easily formed. For example, the specific resistance is 30 ~ tungsten silicide
100μΩcm, molybdenum silicide 40 to 100μΩ
cm, tantalum silicide is 30 to 60 μΩcm, and titanium silicide is 13 to 30 μΩcm.

シリサイドを素子に用いる場合、シリサイド単
層で用いる場合と、シリサイド層の下に多結晶珪
素を敷く所謂ポリサイド構造をとる場合がある。
ポリサイド構造は複合層のため、微細パターン形
成のエツチング条件の設定が難しい。しかしポリ
サイド構造は珪素とオーム接合が形成され易く、
珪素基板または二酸化珪素膜と接する部分が多結
晶珪素であるため、実績のあるプロセスで、素子
特性例えばしきい値電圧、立ち上がり電圧等は従
来と変わらず、また半導体素子製作上最も複雑
で、問題の多い界面についても新たな問題を引き
起こす心配は少ない。
When silicide is used in an element, it may be used as a single layer of silicide, or it may have a so-called polycide structure in which polycrystalline silicon is laid under a silicide layer.
Since the polycide structure is a composite layer, it is difficult to set etching conditions for forming fine patterns. However, the polycide structure tends to form ohmic junctions with silicon.
Since the part in contact with the silicon substrate or silicon dioxide film is polycrystalline silicon, it is a proven process, and device characteristics such as threshold voltage and rise voltage remain the same as before. There is little concern that new problems will occur with respect to interfaces with many .

(c) 従来技術と問題点 高融点金属としてタングステン、下地として珪
素基板またはその上に被着された二酸化珪素層を
用い、高融点金属シリサイド層形成の従来技術を
つぎに説明する。
(c) Prior Art and Problems A conventional technique for forming a high melting point metal silicide layer using tungsten as the high melting point metal and a silicon substrate or a silicon dioxide layer deposited thereon as the base will be described below.

i スバツタ法 珪素または多結晶珪素の上に直接金属を被着
し、高温処理で反応させてシリサイド層を形成す
る。また珪素と金属を同時に被着させる方法もよ
く用いられる。この場合金属、珪素の被着方法と
してスパツタ、蒸着、鍍金等があるが、ここでは
スバツタで代表させる。
i Svatuta method A metal is deposited directly on silicon or polycrystalline silicon and reacted with high temperature treatment to form a silicide layer. A method of simultaneously depositing silicon and metal is also often used. In this case, methods for depositing metal and silicon include sputtering, vapor deposition, plating, etc., but sputtering is used here as a representative example.

スパツタによる被着は方向性があるため段差被
覆が悪い。またスパツタのターゲツトとして用い
る高融点金属中に微量のウラン、トリウム等の放
射性元素を含み、これらの不純物が配線材料中に
含まれることによる半導体装置特にメモリ素子の
α線障害による記憶情報の喪失、所謂ソフトエラ
ーを起こすことがある。
Spatter adhesion is directional, so step coverage is poor. In addition, the high melting point metal used as a sputtering target contains trace amounts of radioactive elements such as uranium and thorium, and these impurities are included in wiring materials, resulting in loss of stored information due to α-ray damage in semiconductor devices, especially memory elements. A so-called soft error may occur.

六弗化タングステンとモノシランによる減圧
気相成長法 チヤンバー中に六弗化タングステンとモノシラ
ンを別々に導入し、チヤンバー中で混合し、300
〜450℃で反応させてシリサイド層を形成する。
この場合は上記ガス混合の近傍のみシリサイド層
の形成が行われ、多数の半導体ウエハにシリサイ
ド層を形成することは困難であり、従つて量産は
できない。
Low pressure vapor phase growth method using tungsten hexafluoride and monosilane Tungsten hexafluoride and monosilane were introduced separately into the chamber, mixed in the chamber,
React at ~450°C to form a silicide layer.
In this case, the silicide layer is formed only in the vicinity of the gas mixture, and it is difficult to form the silicide layer on a large number of semiconductor wafers, so mass production is not possible.

(d) 発明の目的 本発明の目的は従来技術の有する上記の欠点を
除去し、剥離し難く、段差被覆がよく、α線障害
がなく、多数の基板を同時に形成できる量産効果
の大きい高融点金属シリサイド層の形成方法を提
供することにある。
(d) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a high melting point material that is difficult to peel off, provides good step coverage, is free from α-ray damage, and has a large mass production effect that allows the simultaneous formation of a large number of substrates. An object of the present invention is to provide a method for forming a metal silicide layer.

(e) 発明の構成 上記目的は本発明によれば、下地の上に、多結
晶珪素層、水素化アモルフアス珪素層を順次被着
し、該水素化アモルフアス珪素層をフツ素を含む
高融点金属の化合物ガスと反応させて高融点金属
シリサイド層を形成し、該多結晶珪素層とその上
に被着された該高融点金属シリサイド層との複合
膜を形成することによつて達成される。
(e) Structure of the Invention According to the present invention, the above object is to sequentially deposit a polycrystalline silicon layer and a hydrogenated amorphous silicon layer on a base, and replace the hydrogenated amorphous silicon layer with a high melting point metal containing fluorine. This is achieved by forming a high melting point metal silicide layer by reacting with a compound gas, and forming a composite film of the polycrystalline silicon layer and the high melting point metal silicide layer deposited thereon.

本発明はアモルフアス珪素中には多量の水素が
含まれ、このためシリサイド形成が容易に行われ
ることを利用したものである。
The present invention utilizes the fact that amorphous silicon contains a large amount of hydrogen, and therefore silicide formation is easily carried out.

例えばタングステンの場合はつぎの反応式で容
易にタングステン・シリサイド(SixWy)ができ
る。
For example, in the case of tungsten, tungsten silicide (Si x W y ) can be easily produced using the following reaction formula.

SiH+WF6→SixWy+HF Si+WF6→W+SiF6 (f) 発明の実施例 第1図は本発明の実施例を示す断面である。図
において1は下地、2は多結晶珪素層、3はアモ
ルフアス珪素層を示す。
SiH+WF 6 →Si x W y +HF Si+WF 6 →W+SiF 6 (f) Embodiment of the Invention FIG. 1 is a cross section showing an embodiment of the invention. In the figure, 1 is a base, 2 is a polycrystalline silicon layer, and 3 is an amorphous silicon layer.

第1図aにおいて、下地1として珪素基板上に
被着された二酸化珪素層を用い、その上に厚さ
2000Åのドープした多結晶珪素層2を620℃で通
常の気相成長法により被着する。この層の形成は
下地との密着性をよくし、かつ前記の理由により
種々の利点をもつために行う。
In FIG. 1a, a silicon dioxide layer deposited on a silicon substrate is used as the base 1, and a thickness of
A 2000 Å doped polycrystalline silicon layer 2 is deposited at 620° C. by conventional vapor deposition. This layer is formed to improve adhesion to the base and to provide various advantages for the reasons mentioned above.

つぎにプラズマ気相成長法により、厚さ2000〜
3000Åのアモルフアス珪素層3を被着する。
Next, by plasma vapor deposition method, a thickness of 2000~
A 3000 Å amorphous silicon layer 3 is deposited.

プラズマ気相成長は、第2図において、容器2
1中に置かれた珪素基板22を接地し、かつ450
℃に加熱し、アルゴンで1〜5%に希釈したモノ
シランを容器21内に導入し、13.56MHzまたは
数100KHzの電源23を対向電極24に接続して
電力を数10〜数100W加えて行う。
In FIG. 2, plasma vapor phase growth is performed in a container 2
The silicon substrate 22 placed in 1 is grounded, and 450
Monosilane heated to 0.degree. C. and diluted to 1 to 5% with argon is introduced into the container 21, a 13.56 MHz or several 100 KHz power source 23 is connected to the counter electrode 24, and a power of several 10 to several 100 W is applied.

アモルフアス珪素層3を成長後クリーニング・
ガスとして5〜20%の酸素を含んだ四弗化炭素ま
たは三弗化窒素を流して洗浄する。
Cleaning the amorphous silicon layer 3 after growth
Cleaning is performed by flowing carbon tetrafluoride or nitrogen trifluoride containing 5 to 20% oxygen as a gas.

第1図bにおいて、アモルフアス珪素層3を六
弗化タングステンと反応させ、タングステン・シ
リサイド層3Aに変換する。
In FIG. 1b, the amorphous silicon layer 3 is reacted with tungsten hexafluoride and converted into a tungsten silicide layer 3A.

この反応に用いる装置は通常の気相成長装置
で、第3図に示す。図において、31は容器、3
2は基板、33はヒータを示す。
The apparatus used for this reaction is an ordinary vapor phase growth apparatus, as shown in FIG. In the figure, 31 is a container, 3
2 is a substrate, and 33 is a heater.

容器31内に多数の基板32を並べ容器内を
0.2〜0.3Torrに排気し、これらをヒータ32によ
り300〜500℃に加熱し、流量30c.c./分の六弗化タ
ングステンと200c.c./分の水素を混合して導入す
る。また別の導入口より、六弗化タングステンを
薄め、かつ容器内均等に配分する役目をするキヤ
リア・ガスとして800c.c./分の窒素を流す。
A large number of substrates 32 are arranged in a container 31, and the inside of the container is
The mixture is evacuated to 0.2 to 0.3 Torr, heated to 300 to 500° C. by a heater 32, and a mixture of tungsten hexafluoride and hydrogen at a flow rate of 30 c.c./min and 200 c.c./min is introduced. From another inlet, 800 c.c./min of nitrogen is flowed as a carrier gas, which serves to dilute the tungsten hexafluoride and distribute it evenly within the container.

水素は実施例のように、下地が二酸化珪素層の
場合は省略してもよいが、下地が珪素の場合は下
地の浸食防止のために必要となる。
Hydrogen may be omitted when the base is a silicon dioxide layer as in the embodiment, but when the base is silicon, it is necessary to prevent erosion of the base.

実施例では下地として二酸化珪素層を用いた
が、これを珪素または二酸化珪素と珪素の両方
を、あるいは他の材料をもちいてもよい。
In the embodiment, a silicon dioxide layer is used as the base, but silicon, both silicon dioxide and silicon, or other materials may be used.

また実施例では高融点金属としてタングステン
を用いたが、これを他の金属例えばモリブデン等
を用いても発明の要旨は変わらない。
Furthermore, although tungsten was used as the high melting point metal in the embodiment, the gist of the invention would not change even if other metals such as molybdenum were used instead.

(g) 発明の効果 以上詳細に説明したように本発明によれば、剥
離し難く、段差被覆がよく、α線障害がなく、多
数の基板を同時に形成できる最産効果の大きい高
融点金属シリサイド層の形成方法を提供すること
ができる。
(g) Effects of the Invention As explained in detail above, according to the present invention, a high melting point metal silicide is difficult to peel off, has good step coverage, is free from α-ray damage, and has a great productivity effect, allowing the simultaneous formation of a large number of substrates. A method of forming a layer can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す基板断面、第2
図はアモルフアス珪素層形成装置、第3図はシリ
サイド層形成装置を示す。 図において1は下地、2は多結晶珪素層、3は
アモルフアス珪素層、3Aはシリサイド層、21
は容器、22は珪素基板、23は電源、24は電
極、31は容器、32は基板、33はヒータを示
す。
FIG. 1 is a cross section of a substrate showing an embodiment of the present invention, and FIG.
The figure shows an amorphous silicon layer forming apparatus, and FIG. 3 shows a silicide layer forming apparatus. In the figure, 1 is a base layer, 2 is a polycrystalline silicon layer, 3 is an amorphous silicon layer, 3A is a silicide layer, 21
2 is a container, 22 is a silicon substrate, 23 is a power source, 24 is an electrode, 31 is a container, 32 is a substrate, and 33 is a heater.

Claims (1)

【特許請求の範囲】[Claims] 1 下地の上に、多結晶珪素層、水素化アモルフ
アス珪素層を順次被着し、該水素化アモルフアス
珪素層をフツ素を含む高融点金属の化合物ガスと
反応させて高融点金属シリサイド層を形成し、該
多結晶珪素層とその上に被着された該高融点金属
シリサイド層との複合膜を形成することを特徴と
する半導体装置の製造方法。
1. A polycrystalline silicon layer and a hydrogenated amorphous silicon layer are sequentially deposited on the base, and the hydrogenated amorphous silicon layer is reacted with a high melting point metal compound gas containing fluorine to form a high melting point metal silicide layer. and forming a composite film of the polycrystalline silicon layer and the refractory metal silicide layer deposited thereon.
JP3352884A 1984-02-24 1984-02-24 Manufacture of semiconductor device Granted JPS60178642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3352884A JPS60178642A (en) 1984-02-24 1984-02-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3352884A JPS60178642A (en) 1984-02-24 1984-02-24 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS60178642A JPS60178642A (en) 1985-09-12
JPH0530055B2 true JPH0530055B2 (en) 1993-05-07

Family

ID=12389045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3352884A Granted JPS60178642A (en) 1984-02-24 1984-02-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60178642A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6315418A (en) * 1986-07-08 1988-01-22 Fujitsu Ltd Manufacture of semiconductor device
US4737474A (en) * 1986-11-17 1988-04-12 Spectrum Cvd, Inc. Silicide to silicon bonding process
JPS63260052A (en) * 1987-04-03 1988-10-27 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its manufacture

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698872A (en) * 1980-01-07 1981-08-08 Nec Corp Preparation of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698872A (en) * 1980-01-07 1981-08-08 Nec Corp Preparation of semiconductor device

Also Published As

Publication number Publication date
JPS60178642A (en) 1985-09-12

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