JPS63260052A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce a warp of a wafer and to decrease stress applied to a polycide electrode and to improve electrical characteristics and reliability, by piling amorphous silicon and polycrystalline silicon serially on an Si substrate and next performing heat treatment. CONSTITUTION:A SiO2 film 3 is formed on an Si substrate 4. Next, a polycrystalline silicon 2 is piled on the film 3 and impurities are injected into this polycrystalline silicon film 2 and amorphous silicon film 6 is piled on the film 2. Thereafter Mo 1 is evaporated on the film 6 and heat treatment is performed to form a MoSi2 film 5. Then, the MoSi2 film 5 whose thickness is about twice that of the Mo 1 film is formed in a film 7 which is made by polycrystallization of amorphous silicon 6 provided with heat treatment. According to this process, stress-free polycide structure without a warp of the wafer can be easily obtained by selecting a film thickness ratio of polycrystalline silicon to amorphous silicon in conformity with the film stress of the MoSi2 film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a method for forming a high quality and highly reliable polycide electrode.

[Conventional technology]

As LSIs become smaller, gate electrode wiring resistance increases, resulting in a delay in signal propagation time. This structure (upper silicide, lower polyshincon) is attracting attention. When forming polycide structures, methods using alloy reaction methods have been widely used since the process is simple.
This formation method is shown in FIG. Here, 1 is Mo and 2 is polycrystalline silicon.

3 is 5i01 film, 4 is St substrate, 5 is '? 1oSi.

In this method, as shown in Figure 1, polycrystalline silicon and metal films are deposited on a Si substrate (Figure 1 [α)]), and heat treatment is performed after ion implantation (Figure 1 (b)). Yes (Figure 1 (C)). In this method, S
Film stress is generated due to the difference in thermal expansion coefficient between the i-substrate, polycrystalline silicon layer, and silicide layer, so the wafer tends to be concave or convex.Film stress also depends on heat treatment conditions and silicide film thickness. do. For this reason, the film thickness structure of silicide and polycrystalline silicon, the heat treatment conditions cannot be limited to the optimum range, the photo process becomes difficult due to the wafer thickness, and as the film stress increases, dislocations occur in the gate oxide film.
It is known that defects occur and change the electrical characteristics of the gate oxide film. Further, if the warpage of the wafer due to film stress is the same, the film stress becomes larger as the film thickness becomes thinner. As gate oxide films become thinner with miniaturization,
The increase in film stress caused deterioration of device characteristics, such as a drop in breakdown voltage of the gate oxide film.

Means for Solving Problem C] Purpose of the Invention The purpose of the present invention is to reduce stress increase due to heat treatment process in polycide electrode formation and increase in silicide film thickness, and to improve electrical characteristics and reliability of polycide electrode. It is to measure.

Structure and operation of the invention When amorphous silicon and polycrystalline silicon are respectively deposited on a Si substrate and heat treated, the wafer on which amorphous silicon is deposited becomes concave, and the wafer on which polycrystalline silicon is deposited is It was found that the curve warped in a convex manner. The feature of the invention is to utilize this phenomenon to sequentially deposit amorphous silicon and polycrystalline silicon on a Si substrate and perform heat treatment to reduce wafer warpage, reduce stress on polycide electrodes, and reduce electrical The aim is to improve physical characteristics and reliability.

In polycide electrode formation technology using the conventional alloy reaction method, the setting range of heat treatment conditions is narrow in order to reduce stress.
Furthermore, it was difficult to increase the silicide film thickness. In the method of the present invention, wafer warpage can be reduced by optimizing the film thickness ratio of amorphous silicon and polycrystalline silicon according to the stress of the silicide layer film under certain heat treatment conditions. It is. Therefore, the setting range of heat treatment conditions is wide, and since the silicide film thickness can be increased, the process margin can be expanded and the resistance of the gate electrode wiring can be lowered.

Example FIG. 2 shows the experimental results that form the basis of the present invention.

Figure 2 shows polycrystalline silicon and amorphous silicon in sequence.
Deposited on the substrate, the gate electrode film thickness was 3000 x 90 by changing the film thickness ratio of crystalline silicon and amorphous silicon.
Heat treatment was performed at 0°C for 30 minutes to form a gate oxide film (74A
) shows the change in membrane stress applied to the film.

It can be seen from FIG. 2 that the film stress in the υ gate oxide film can be reduced by optimizing the film thickness ratio of polycrystalline silicon and amorphous silicon. Here, polycrystalline silicon was formed by a CVD method in which monosilane was thermally decomposed at a temperature of 625°C, and amorphous silicon was formed by a CVD method in which disilane was thermally decomposed at a temperature of 525°C. Furthermore, when polycrystalline silicon and amorphous silicon are subjected to electron beam diffraction, the diffraction patterns become ring-shaped and halo-shaped, respectively.

FIG. 3 shows a case where the present invention is applied to a polycide electrode. Here, 6 is amorphous silicon, and 7 is a film in which the amorphous silicon is made polycrystalline by heat treatment. First, a 5iO1 film 3 (70A') is formed on the S (FIG. 5a).

Next, polycrystalline silicon 2 (20001) is deposited, and after doping impurities (boron, phosphorus, etc.) into the polycrystalline silicon 2 film, amorphous silicon 6 (1000A) is deposited (third
Figure b). Thereafter, Mo 1 (400 A) is deposited and heat treated (900° C., 30 minutes) to form a Mo S t 2 film 5 (800 A) (FIG. 3G). At this time, a MoSi2 film 5 having a thickness approximately twice as thick as one Mo film is formed in the pattern 7 in which the amorphous silicon 6 is polycrystalized by heat treatment. Further, the grain boundaries of the film 7 in which amorphous silicon is made polycrystalline by heat treatment are about 1000A, which is characterized by being larger than the grain boundaries 600A of the polycrystalline silicon 2 film. According to this process, by selecting the film thickness ratio of polycrystalline silicon and amorphous silicon in accordance with the film stress of the MoSi2 film 5, a stress-free polycide structure that does not cause wafer warping can be easily obtained. It will be done. Note that Fig. 5 shows an example of a silicide film Mo5L* film under heat treatment conditions of 900°C for 30 minutes, but since the stress value depends on the heat treatment conditions and the type of silicide layer, there are no measures to reduce the film stress. The optimum film thickness ratio may be determined depending on the heat treatment conditions used in the process and the film stress of the silicide layer. In the above embodiments, a case has been described in which amorphous silicon is formed on polycrystalline silicon, but conversely, a case in which polycrystalline silicon is formed on amorphous silicon may be used. Moreover, it goes without saying that the structure does not have to be two layers, but may be a multilayer structure that satisfies stress-free conditions.

Effects of the Invention As shown in the examples, when polycrystalline silicon and amorphous silicon are deposited on a S<substrate and heat treated, the warpage of the wafer becomes smaller and the film stress of the gate oxide film can be reduced. I can do it. For this reason, it is possible to increase the silicide thickness in the polycide gate electrode process υ, resulting in a low-resistance polysilicon gate electrode, and the gate oxide film can be thinned with low film stress. This has the advantage of improved reliability.

[Brief explanation of drawings]

Figure 1 shows a polycide electrode formation method using a conventional alloy reaction method. FIG. 2 shows changes in film stress applied to the gate oxide film as a result of changing the film thickness ratio of amorphous silicon/polycrystalline silicon. FIG. 3 shows a polycide electrode formed by the method of the present invention. In the figure, 1...V (12...polycrystalline silicon 6...5i
02 film 4...Si substrate 5...AloSs2
6... Amorphous silicon 7... Amorphous silicon becomes polycrystalline due to heat treatment and agent Patent attorney Gobe Tamamushi (
+1111 Ion implantation alloy reaction method

Claims (2)

[Claims] (1) A first polycrystalline silicon film and a second polycrystalline film having a larger grain size (grain boundary) than the polycrystalline silicon produced by heat-treating amorphous silicon in random order, at least two
A semiconductor device characterized by having a polycide structure consisting of a polycrystalline composite film composed of layers and a metal silicide formed on the polycrystalline composite film. (2) A process of forming amorphous silicon on polycrystalline silicon, or a process of forming a metal film on a two-layer structure obtained by forming polycrystalline silicon on amorphous silicon, and applying heat treatment. A semiconductor device manufacturing method characterized by comprising: