JPS54159185A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54159185A
JPS54159185A JP6851278A JP6851278A JPS54159185A JP S54159185 A JPS54159185 A JP S54159185A JP 6851278 A JP6851278 A JP 6851278A JP 6851278 A JP6851278 A JP 6851278A JP S54159185 A JPS54159185 A JP S54159185A
Authority
JP
Japan
Prior art keywords
layer
dielectric strength
substrate
concentration
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6851278A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6851278A priority Critical patent/JPS54159185A/en
Publication of JPS54159185A publication Critical patent/JPS54159185A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To establish MOSFET of high dielectric strength, by providing the low concentration layer from the substrate in the semiconductor substrate under the opening of insulation film. CONSTITUTION:The SiO2 film 13 of the P<+> substrate 10 is opened and the P layer 17 is formed with N type ion injection. The concentration and depth of the layer 17 can be determined by referencing the depth of the next N<+> diffusion. Further, the P<-> epitaxial layer 12, gate oxide film 13, and polycrystal Si gate electrode 14 are formed selectively. Succeedingly, the electrode 14 is made conductive with the N<+> diffusion to form the N<+> layers 15 and 16. In this case, even if the N<+> layers 15 and 16 are extended to the P<+> substrate side, the junction is formed with the N<+> layer and the P layer 17. Since the layer 17 is selected with the concentration to obtain desired greater dielectric strength, the increase in the junction capacitance and the lowering in the source and drain dielectric strength as conventional devices can not be taken place.
JP6851278A 1978-06-07 1978-06-07 Semiconductor device Pending JPS54159185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6851278A JPS54159185A (en) 1978-06-07 1978-06-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6851278A JPS54159185A (en) 1978-06-07 1978-06-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54159185A true JPS54159185A (en) 1979-12-15

Family

ID=13375835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6851278A Pending JPS54159185A (en) 1978-06-07 1978-06-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54159185A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55111178A (en) * 1979-02-20 1980-08-27 Mitsubishi Electric Corp Field-effect semiconductor device
EP0436038A1 (en) * 1989-07-14 1991-07-10 SEIKO INSTRUMENTS &amp; ELECTRONICS LTD. Semiconductor device and method of producing the same
US5347151A (en) * 1990-12-06 1994-09-13 Mitsubishi Denki Kabushiki Kaisha DRAM with memory cells having access transistor formed on solid phase epitaxial single crystalline layer and manufacturing method thereof
US5672530A (en) * 1993-03-22 1997-09-30 Sharp Microelectronics Technology, Inc. Method of making MOS transistor with controlled shallow source/drain junction

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55111178A (en) * 1979-02-20 1980-08-27 Mitsubishi Electric Corp Field-effect semiconductor device
EP0436038A1 (en) * 1989-07-14 1991-07-10 SEIKO INSTRUMENTS &amp; ELECTRONICS LTD. Semiconductor device and method of producing the same
US5347151A (en) * 1990-12-06 1994-09-13 Mitsubishi Denki Kabushiki Kaisha DRAM with memory cells having access transistor formed on solid phase epitaxial single crystalline layer and manufacturing method thereof
US5672530A (en) * 1993-03-22 1997-09-30 Sharp Microelectronics Technology, Inc. Method of making MOS transistor with controlled shallow source/drain junction
US5932913A (en) * 1993-03-22 1999-08-03 Sharp Microelectronics Technology, Inc. MOS transistor with controlled shallow source/drain junction, source/drain strap portions, and source/drain electrodes on field insulation layers

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