JPS54102877A - Field effect transistor - Google Patents

Abstract

PURPOSE: To establish short channel FET, by providing the diffusion layer of the same conduction type as the lower layer from the upper layer to the lower layer of two types of conductive layers, and by providing the diffusion layer of the same conduction type as the upper layer from the window.

CONSTITUTION: The P epitaxial layer 12 is formed on the N type substrate 11, and the P type layer 14 is formed shallower than the layer 13 from the diffusion window the same as the N type diffusion layer 13 reaching the substrate 11 from the surface. The layer 13 is connected to the substrate 11. Thus, the layer 13 is the channel, external of the layer 13 is the source, the substrate 11 is the drain, and the layers 12 and 14 are the gates. The N⁺ layer 15 reduces the drain series resistance. The channel thickness is formed accurately with the difference of the diffusion depth, the length L can be made shorter by taking the thickness of the layer 12 thin, and the concentration of the layer 13 is increased, allowing to increase gm. Further, the gate and drain dielectric strength can be made higher by making smaller the concentration of the layer 11.

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