JPS6421969A - Vertical type mosfet device and manufacture thereof - Google Patents

Vertical type mosfet device and manufacture thereof

Info

Publication number
JPS6421969A
JPS6421969A JP62177281A JP17728187A JPS6421969A JP S6421969 A JPS6421969 A JP S6421969A JP 62177281 A JP62177281 A JP 62177281A JP 17728187 A JP17728187 A JP 17728187A JP S6421969 A JPS6421969 A JP S6421969A
Authority
JP
Japan
Prior art keywords
layer
groove
polycrystalline
substrate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62177281A
Other languages
Japanese (ja)
Inventor
Hirohisa Kitaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62177281A priority Critical patent/JPS6421969A/en
Publication of JPS6421969A publication Critical patent/JPS6421969A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To reduce the resistance of a gate polycrystalline Si layer as a surface step is made small, to lessen a time constant and to make it possible to improve high-frequency characteristics by a method wherein the gate polycrystalline Si layer is isolated by the surface of a semiconductor substrate and a groove part and the gate polycrystalline Si layer is provided in the groove part in such away as to fill the groove part. CONSTITUTION:A second conductivity type first impurity diffused layer 13 is formed on the surface parts of first conductivity type semiconductor substrates 11 and 12 and a first conductivity type second impurity diffused layer 14 is formed shallowly in the layer 13. A groove 20, which penetrates the layer 14 and the above layer 13 and reaches to the substrate part 12, is formed in part of the layer 14, gate oxide film layers 21 and 15 are formed on the inner wall of the groove 20 and the surface of the substrate 12 and a first polycrystalline Si layer 16 is formed on the layer 15 on the surface of the substrate. Moreover, a second polycrystalline Si layer 22, which is connected electrically with the above layer 16 and constitutes a gate polycrystalline Si layer along with the layer 16, is formed in the groove 20 in such a way as to fill the interior of the groove 20.
JP62177281A 1987-07-17 1987-07-17 Vertical type mosfet device and manufacture thereof Pending JPS6421969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62177281A JPS6421969A (en) 1987-07-17 1987-07-17 Vertical type mosfet device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62177281A JPS6421969A (en) 1987-07-17 1987-07-17 Vertical type mosfet device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6421969A true JPS6421969A (en) 1989-01-25

Family

ID=16028296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62177281A Pending JPS6421969A (en) 1987-07-17 1987-07-17 Vertical type mosfet device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6421969A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891343A (en) * 1988-08-10 1990-01-02 W. R. Grace & Co.-Conn. Stabilized zirconia

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4891343A (en) * 1988-08-10 1990-01-02 W. R. Grace & Co.-Conn. Stabilized zirconia

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