JPS5698871A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5698871A
JPS5698871A JP42080A JP42080A JPS5698871A JP S5698871 A JPS5698871 A JP S5698871A JP 42080 A JP42080 A JP 42080A JP 42080 A JP42080 A JP 42080A JP S5698871 A JPS5698871 A JP S5698871A
Authority
JP
Japan
Prior art keywords
layer
electrode
platinum
type
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP42080A
Other languages
Japanese (ja)
Inventor
Hiroki Muta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP42080A priority Critical patent/JPS5698871A/en
Publication of JPS5698871A publication Critical patent/JPS5698871A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To improve yield, by making both the electrode that forms the Schottky barrier and the source and drain electrode for ohmic contact using platinum silicide layer and by consituting the wire that is connected to them by the double layers of the platinum silicide layer and the platinum layer.
CONSTITUTION: On the P type Si substrate 31, the device separation layer 32, the P+ type region 33 as the channel stopper and the N+ type layers 34a, 34b and 34c which correspond to the source and drain regions are formed, and the N type layer 35 is further formed as the active layer. Next, the gate electrode 36a and 36b as the Schottky junction and the ohmic electrode 36 to the source and drain regions are formed. These are made of platinum silicide. The wires 37 that extend from each of these electrode and the wires among the layers are made of platinum silicide for the upper side and of platinum layer 38 for the lower side. Thus, the wires for at least a layer can be spared resulting in the higher integration.
COPYRIGHT: (C)1981,JPO&Japio
JP42080A 1980-01-07 1980-01-07 Integrated circuit Pending JPS5698871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP42080A JPS5698871A (en) 1980-01-07 1980-01-07 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP42080A JPS5698871A (en) 1980-01-07 1980-01-07 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS5698871A true JPS5698871A (en) 1981-08-08

Family

ID=11473303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP42080A Pending JPS5698871A (en) 1980-01-07 1980-01-07 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5698871A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916383A (en) * 1982-07-19 1984-01-27 Sony Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514627A (en) * 1974-07-03 1976-01-14 Shoketsu Kinzoku Kogyo Kk Pairotsutoshiki 2 hokodenjiben

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514627A (en) * 1974-07-03 1976-01-14 Shoketsu Kinzoku Kogyo Kk Pairotsutoshiki 2 hokodenjiben

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916383A (en) * 1982-07-19 1984-01-27 Sony Corp Semiconductor device

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