JPS6410673A - Non volatile semiconductor memory device - Google Patents

Non volatile semiconductor memory device

Info

Publication number
JPS6410673A
JPS6410673A JP62165974A JP16597487A JPS6410673A JP S6410673 A JPS6410673 A JP S6410673A JP 62165974 A JP62165974 A JP 62165974A JP 16597487 A JP16597487 A JP 16597487A JP S6410673 A JPS6410673 A JP S6410673A
Authority
JP
Japan
Prior art keywords
gate electrode
trench
floating gate
insulating film
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62165974A
Other languages
Japanese (ja)
Inventor
Akihiko Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP62165974A priority Critical patent/JPS6410673A/en
Publication of JPS6410673A publication Critical patent/JPS6410673A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To reduce the uneven step-difference on a substrate surface caused by a gate electrode, improve the quality of an insulating film and a wiring on the element region, and increase the reliability, by burying a floating gate electrode in a substrate between source and drain regions, via a gate insulating film. CONSTITUTION:As to an EPROM cell structure having a floating gate electrode, a floating gate electrode 7 is buried in a trench 5 via a gate insulating film 6. The trench is arranged in an exposed portion of a P<-> type silicon substrate surface 1 and defined by a field insulating film 2. A memory cell is constituted of a source region 8 and a drain region 9 of n<+> type which are arranged in the semiconductor surface 1 on both sides of the trench 5 and separated by the trench 5, and whose bottom parts reach the lower region of the floating gate electrode 7. As the floating gate electrode is buried in the trench 5 in this manner, the uneven step-difference on the cell surface caused by the gate electrode can be remarkably reduced.
JP62165974A 1987-07-02 1987-07-02 Non volatile semiconductor memory device Pending JPS6410673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165974A JPS6410673A (en) 1987-07-02 1987-07-02 Non volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165974A JPS6410673A (en) 1987-07-02 1987-07-02 Non volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS6410673A true JPS6410673A (en) 1989-01-13

Family

ID=15822538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165974A Pending JPS6410673A (en) 1987-07-02 1987-07-02 Non volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS6410673A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03233974A (en) * 1990-02-08 1991-10-17 Matsushita Electron Corp Manufacture of nonvolatile semiconductor memory
JPH03257873A (en) * 1990-03-07 1991-11-18 Matsushita Electron Corp Non-volatile semiconductor memory device and manufacture thereof
US5359218A (en) * 1991-10-03 1994-10-25 Kabushiki Kaisha Toshiba Semiconductor memory device with selection gate in a groove
FR2807208A1 (en) * 2000-03-29 2001-10-05 St Microelectronics Sa Non-volatile memory semiconductor device has floating gate extending between the source and drain regions, and control gate situated above floating gate
JP2014531140A (en) * 2011-10-28 2014-11-20 インヴェンサス・コーポレイション Vertical drain-gate capacitively coupled nonvolatile memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03233974A (en) * 1990-02-08 1991-10-17 Matsushita Electron Corp Manufacture of nonvolatile semiconductor memory
JPH03257873A (en) * 1990-03-07 1991-11-18 Matsushita Electron Corp Non-volatile semiconductor memory device and manufacture thereof
US5359218A (en) * 1991-10-03 1994-10-25 Kabushiki Kaisha Toshiba Semiconductor memory device with selection gate in a groove
FR2807208A1 (en) * 2000-03-29 2001-10-05 St Microelectronics Sa Non-volatile memory semiconductor device has floating gate extending between the source and drain regions, and control gate situated above floating gate
US6642108B2 (en) 2000-03-29 2003-11-04 Stmicroelectronics Sa Fabrication processes for semiconductor non-volatile memory device
JP2014531140A (en) * 2011-10-28 2014-11-20 インヴェンサス・コーポレイション Vertical drain-gate capacitively coupled nonvolatile memory device

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