JPS5623739A - Manufactue of semiconductor element having buried layer - Google Patents

Manufactue of semiconductor element having buried layer

Info

Publication number
JPS5623739A
JPS5623739A JP9913579A JP9913579A JPS5623739A JP S5623739 A JPS5623739 A JP S5623739A JP 9913579 A JP9913579 A JP 9913579A JP 9913579 A JP9913579 A JP 9913579A JP S5623739 A JPS5623739 A JP S5623739A
Authority
JP
Japan
Prior art keywords
type
layer
density
plane
compensating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9913579A
Other languages
Japanese (ja)
Other versions
JPS576685B2 (en
Inventor
Tomio Kazono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tohoku Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tohoku Metal Industries Ltd filed Critical Tohoku Metal Industries Ltd
Priority to JP9913579A priority Critical patent/JPS5623739A/en
Publication of JPS5623739A publication Critical patent/JPS5623739A/en
Publication of JPS576685B2 publication Critical patent/JPS576685B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain the extremely effective buried gate in the semiconductor element by epitaxially growing an n-type compensating layer and a low density n-type layer lower in density than the compensating layer continuously on an i or n<->-type layer and n<+>-type layer buried therein. CONSTITUTION:An i or n<->-type epitaxial layer 2 and an SiO2 film 3 are superimposed on an n<+>-type Si substrate 1, and openings 3a are perforated in striped state. Then, a p<+>-type buried gate 4 is formed thereon, an SiO2 film 5 on the surface is etched, and a thin n-type compensating layer 10 and a low density n-type layer 6 lower in density than the compensating layer 10 are continuously epitaxially grown in vapor phase and laminated. In this case, the vapor phase growing temperature x is located in a plane yz at 1,100 deg.C and 1,150 deg.C, and when the compensating layer 10 is formed under the conditions contained in the region formed by a curved plane including accumulated gas flow amount y=0.9(l/min) in a plane zx and diffusing surface density z=5X10<18>/cm<3> in a plane xy, and definite point A (1,100, 0.90, 1.5X10<19>)-H(1,150, 1.10, 8.5X10<18>), it can prevent the channel inversion and there can be obtained the accurate buried gate layer with preferable reproducibility.
JP9913579A 1979-08-04 1979-08-04 Manufactue of semiconductor element having buried layer Granted JPS5623739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9913579A JPS5623739A (en) 1979-08-04 1979-08-04 Manufactue of semiconductor element having buried layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9913579A JPS5623739A (en) 1979-08-04 1979-08-04 Manufactue of semiconductor element having buried layer

Publications (2)

Publication Number Publication Date
JPS5623739A true JPS5623739A (en) 1981-03-06
JPS576685B2 JPS576685B2 (en) 1982-02-06

Family

ID=14239278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9913579A Granted JPS5623739A (en) 1979-08-04 1979-08-04 Manufactue of semiconductor element having buried layer

Country Status (1)

Country Link
JP (1) JPS5623739A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6216578A (en) * 1985-07-15 1987-01-24 Toyo Electric Mfg Co Ltd Manufacture of semiconductor element substrate with buried layer
JPH03161248A (en) * 1989-11-15 1991-07-11 Okuma Mach Works Ltd Indexing control device for tool rest of nc lathe
WO2002079551A1 (en) * 2001-03-30 2002-10-10 Koninklijke Philips Electronics N.V. Suppression of n-type autodoping in low-temperature si and sige epitaxy

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3660180A (en) * 1969-02-27 1972-05-02 Ibm Constrainment of autodoping in epitaxial deposition
US3669769A (en) * 1970-09-29 1972-06-13 Ibm Method for minimizing autodoping in epitaxial deposition
US3847686A (en) * 1970-05-27 1974-11-12 Gen Electric Method of forming silicon epitaxial layers
JPS53135571A (en) * 1977-05-02 1978-11-27 Hitachi Ltd Vapor phase growth method for semiconductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3660180A (en) * 1969-02-27 1972-05-02 Ibm Constrainment of autodoping in epitaxial deposition
US3847686A (en) * 1970-05-27 1974-11-12 Gen Electric Method of forming silicon epitaxial layers
US3669769A (en) * 1970-09-29 1972-06-13 Ibm Method for minimizing autodoping in epitaxial deposition
JPS53135571A (en) * 1977-05-02 1978-11-27 Hitachi Ltd Vapor phase growth method for semiconductor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6216578A (en) * 1985-07-15 1987-01-24 Toyo Electric Mfg Co Ltd Manufacture of semiconductor element substrate with buried layer
JPH03161248A (en) * 1989-11-15 1991-07-11 Okuma Mach Works Ltd Indexing control device for tool rest of nc lathe
WO2002079551A1 (en) * 2001-03-30 2002-10-10 Koninklijke Philips Electronics N.V. Suppression of n-type autodoping in low-temperature si and sige epitaxy
US6838359B2 (en) 2001-03-30 2005-01-04 Koninklijke Philips Electronics N.V. Suppression of n-type autodoping in low-temperature Si and SiGe epitaxy

Also Published As

Publication number Publication date
JPS576685B2 (en) 1982-02-06

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