JPS5623737A - Manufacture of buried type semiconductor element substrate - Google Patents

Manufacture of buried type semiconductor element substrate

Info

Publication number
JPS5623737A
JPS5623737A JP9913379A JP9913379A JPS5623737A JP S5623737 A JPS5623737 A JP S5623737A JP 9913379 A JP9913379 A JP 9913379A JP 9913379 A JP9913379 A JP 9913379A JP S5623737 A JPS5623737 A JP S5623737A
Authority
JP
Japan
Prior art keywords
layer
type
vapor phase
compensating
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9913379A
Other languages
Japanese (ja)
Other versions
JPS572170B2 (en
Inventor
Tomio Kazono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tohoku Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tohoku Metal Industries Ltd filed Critical Tohoku Metal Industries Ltd
Priority to JP9913379A priority Critical patent/JPS5623737A/en
Publication of JPS5623737A publication Critical patent/JPS5623737A/en
Publication of JPS572170B2 publication Critical patent/JPS572170B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain a buried gate of size near the designed value in the semiconductor element substrate by growing in vapor phase beforehand a compensating n-type layer on an i- or n<->-type layer continuously to prevent channel inversion between buried layers. CONSTITUTION:An n<->-type layer 2 and thin n-type layer 10a are superimposed on an n<+>-type Si substrate 1 by a continuous vapor phase epitaxial growing process. Openings 3a are perforated in striped state on an SiO2 film 3 to diffuse p<+>-type layer 4. SiO2 film 5 produced at this time is removed, an n-type layer 6 is formed in vapor phase epitaxially to complete a buried gate layer 4 therein. The thickness of the layer 4 depends upon not only thermal treating condition but the thickness of an n-type compensating layer 10a. When the layer 10a is formed in a thickness of 0.5mu-1mu, the gate layer 4 is reduced from 3mu to 2mu. The n-type impurity density is suitably selected in the compensating layer. This configuration can extremely simply execute the vapor phase growth of the compensating layer, and can form the layers 2 and 10a by continuous vapor phase growth with high workability.
JP9913379A 1979-08-04 1979-08-04 Manufacture of buried type semiconductor element substrate Granted JPS5623737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9913379A JPS5623737A (en) 1979-08-04 1979-08-04 Manufacture of buried type semiconductor element substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9913379A JPS5623737A (en) 1979-08-04 1979-08-04 Manufacture of buried type semiconductor element substrate

Publications (2)

Publication Number Publication Date
JPS5623737A true JPS5623737A (en) 1981-03-06
JPS572170B2 JPS572170B2 (en) 1982-01-14

Family

ID=14239230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9913379A Granted JPS5623737A (en) 1979-08-04 1979-08-04 Manufacture of buried type semiconductor element substrate

Country Status (1)

Country Link
JP (1) JPS5623737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63116250U (en) * 1987-01-22 1988-07-27
JPS63216656A (en) * 1987-03-06 1988-09-08 Toyoda Mach Works Ltd Kinematic error compensation control sliding guide apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63116250U (en) * 1987-01-22 1988-07-27
JPS63216656A (en) * 1987-03-06 1988-09-08 Toyoda Mach Works Ltd Kinematic error compensation control sliding guide apparatus

Also Published As

Publication number Publication date
JPS572170B2 (en) 1982-01-14

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