JPS56158445A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56158445A
JPS56158445A JP6297080A JP6297080A JPS56158445A JP S56158445 A JPS56158445 A JP S56158445A JP 6297080 A JP6297080 A JP 6297080A JP 6297080 A JP6297080 A JP 6297080A JP S56158445 A JPS56158445 A JP S56158445A
Authority
JP
Japan
Prior art keywords
junction
thick
parts
crystal
insulating films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6297080A
Other languages
Japanese (ja)
Inventor
Teruo Kusaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6297080A priority Critical patent/JPS56158445A/en
Publication of JPS56158445A publication Critical patent/JPS56158445A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain the high withstand voltage device with shallow junctions by a method wherein insulating films to cover the bulk surface between the main P-N junction and P-N junction rings for control of electric field, or the bulk surfaces between rings for control of electric field with each other, are formed deeper than the P-N junction face. CONSTITUTION:N type layers 2a, 2b are provided on a P type substrate 1, and the surface of the substrate is covered with thick insulating films 3 and a thin insulating film 4. Openings are formed selectively in the thin film 4 and electrodes 5a, 5b are formed. The layer 2b is formed in a ring shape, the blocking junction and the ring junction have together the passivated mesa structure, and the depth of junction is made as about 1mum. The surface of crystal is an uneven face, and has two kind insulating films of thick and thin. The thick film parts cover and protect the surface parts of the blocking junction and of the ring junction, and the thin film part covers and protects the other crystal face. The thick film parts are provided at the concave parts on the crystal surface to reduce the unevenness of the surface. By this constitution, high blocking withstand voltage can be obtained even with the shallow P-N junction.
JP6297080A 1980-05-13 1980-05-13 Semiconductor device Pending JPS56158445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6297080A JPS56158445A (en) 1980-05-13 1980-05-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6297080A JPS56158445A (en) 1980-05-13 1980-05-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56158445A true JPS56158445A (en) 1981-12-07

Family

ID=13215703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6297080A Pending JPS56158445A (en) 1980-05-13 1980-05-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56158445A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS524433A (en) * 1975-06-30 1977-01-13 Matsushita Electric Works Ltd Composite plating method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS524433A (en) * 1975-06-30 1977-01-13 Matsushita Electric Works Ltd Composite plating method

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