JPS5559761A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5559761A
JPS5559761A JP13153078A JP13153078A JPS5559761A JP S5559761 A JPS5559761 A JP S5559761A JP 13153078 A JP13153078 A JP 13153078A JP 13153078 A JP13153078 A JP 13153078A JP S5559761 A JPS5559761 A JP S5559761A
Authority
JP
Japan
Prior art keywords
grooves
junction
annular
layer
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13153078A
Other languages
Japanese (ja)
Inventor
Masao Tsuruoka
Keiichi Morita
Hideyuki Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13153078A priority Critical patent/JPS5559761A/en
Publication of JPS5559761A publication Critical patent/JPS5559761A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To increase the dielectric strength of a semiconductor device by adhering annular insulator onto the surface of a semiconductor substrate disposed between a plurality of annular grooves exposed at the end of its junction to thereby lengthen the active region distance at the groove portion sintered with glass. CONSTITUTION:An insulator is filled in a plurality of annular grooves exposed at the end of its junction among more than three different conductivity type semiconductor regions of a semiconductor substrate, and an annular insulator is adhered onto the surface of the substrate disposed between the grooves. An outside annular groove 261 exposed at its end 27 of a junction J1 and an inside annular groove 262 exposed at its end 28 of a junction J2 are, for example, formed coaxially at a thyristor semiconductor substrate 21 consisting of a PE layer 22, nB layer 23, PB layer 24 and nE layer 25. Glasses 291, 292 are filled and sintered with the respective grooves 261 and 262, and alumina ring 34 is adhered by an adhesive 35 to the surface 231 of the semiconductor substrate disposed between the grooves 261 and 262.
JP13153078A 1978-10-27 1978-10-27 Semiconductor device Pending JPS5559761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13153078A JPS5559761A (en) 1978-10-27 1978-10-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13153078A JPS5559761A (en) 1978-10-27 1978-10-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5559761A true JPS5559761A (en) 1980-05-06

Family

ID=15060216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13153078A Pending JPS5559761A (en) 1978-10-27 1978-10-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5559761A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111370A (en) * 1981-12-25 1983-07-02 Hitachi Ltd Semiconductor device
JPH01293661A (en) * 1988-05-23 1989-11-27 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111370A (en) * 1981-12-25 1983-07-02 Hitachi Ltd Semiconductor device
JPH01293661A (en) * 1988-05-23 1989-11-27 Nec Corp Semiconductor device

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