JPS5565466A - Mos device - Google Patents
Mos deviceInfo
- Publication number
- JPS5565466A JPS5565466A JP13880578A JP13880578A JPS5565466A JP S5565466 A JPS5565466 A JP S5565466A JP 13880578 A JP13880578 A JP 13880578A JP 13880578 A JP13880578 A JP 13880578A JP S5565466 A JPS5565466 A JP S5565466A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- normal
- poly
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE: To obtain a high-integrated MOS device through a process similar to a normal planer MOS structure as preferring a buried source structure similar basically to MOS structure provided with V-groove.
CONSTITUTION: An n+-layer 12 is formed on p-type Si substrate 11 and after injecting B-ion to form a p+-layer 13, an oxidized film 14 is formed selectively. From forming an epitaxial layer on the overall surface, there obtained are a single crystal layer 21S on the layer 13 and a poly-crystal layer 21P on the film 14. In this case, a domain 22 in the layer 13 works as a channel stopper, and a domain 23 creeps up the layer 21S to make the layer 21S work as a p-layer. Next, the epitaxial layer 21 is openend selectively to form isolating oxidized films 31, 31', and the film 31' is extended to reach the n+-layer 12. Then, gate oxidized films 32-1, 32-2, poly-Si gates 33-1, 33-2 are formed as normal, sources 41-1, 41-2 reaching the n+-layer 12 are formed according to a difference in speed of n+-diffusion, drains 42-1, 42-2 in the same depth as a normal planer type are formed, and a conductivity is given to the Si gate. According to this constitution, a source terminal can be provided only one on the substrate, thus implementing a high integration.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13880578A JPS5565466A (en) | 1978-11-13 | 1978-11-13 | Mos device |
US06/015,427 US4353085A (en) | 1978-02-27 | 1979-02-26 | Integrated semiconductor device having insulated gate field effect transistors with a buried insulating film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13880578A JPS5565466A (en) | 1978-11-13 | 1978-11-13 | Mos device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5565466A true JPS5565466A (en) | 1980-05-16 |
JPS6237820B2 JPS6237820B2 (en) | 1987-08-14 |
Family
ID=15230640
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13880578A Granted JPS5565466A (en) | 1978-02-27 | 1978-11-13 | Mos device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5565466A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4842688A (en) * | 1971-09-27 | 1973-06-21 | ||
JPS4925824U (en) * | 1972-06-10 | 1974-03-05 | ||
JPS5140783A (en) * | 1974-10-03 | 1976-04-05 | Nippon Electric Co | DENKAIKO KAGATAHANDOTAISOCHI |
-
1978
- 1978-11-13 JP JP13880578A patent/JPS5565466A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4842688A (en) * | 1971-09-27 | 1973-06-21 | ||
JPS4925824U (en) * | 1972-06-10 | 1974-03-05 | ||
JPS5140783A (en) * | 1974-10-03 | 1976-04-05 | Nippon Electric Co | DENKAIKO KAGATAHANDOTAISOCHI |
Also Published As
Publication number | Publication date |
---|---|
JPS6237820B2 (en) | 1987-08-14 |
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