JPS5516427A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPS5516427A
JPS5516427A JP8898678A JP8898678A JPS5516427A JP S5516427 A JPS5516427 A JP S5516427A JP 8898678 A JP8898678 A JP 8898678A JP 8898678 A JP8898678 A JP 8898678A JP S5516427 A JPS5516427 A JP S5516427A
Authority
JP
Japan
Prior art keywords
layer
resistance
polysilicon
semiconductor device
drilling holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8898678A
Other languages
Japanese (ja)
Inventor
Kenichi Muramoto
Yutaka Tomizawa
Keizo Tani
Masaaki Iwanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8898678A priority Critical patent/JPS5516427A/en
Publication of JPS5516427A publication Critical patent/JPS5516427A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To improve accuracy of a resistance value of a polysilicon layer and to simplify process by performing the impurities doping of polysilicon before drilling holes for taking out electrodes.
CONSTITUTION: Before drilling holes on an insulating membrane a polysilicon layer 10 will be doped with impurities followed by pattering the said layer 10. By doing so, the resistance value of the said layer will be easily controlled, especially doping ps (layer resistance) can directly measured by a 4-terminals method, theresistance value of resistance layer 10 can be regulated with an extreme accuracy.
COPYRIGHT: (C)1980,JPO&Japio
JP8898678A 1978-07-21 1978-07-21 Method of manufacturing semiconductor device Pending JPS5516427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8898678A JPS5516427A (en) 1978-07-21 1978-07-21 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8898678A JPS5516427A (en) 1978-07-21 1978-07-21 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS5516427A true JPS5516427A (en) 1980-02-05

Family

ID=13958114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8898678A Pending JPS5516427A (en) 1978-07-21 1978-07-21 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5516427A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61219171A (en) * 1985-03-25 1986-09-29 Sanken Electric Co Ltd Multi-cell type transistor
JP2002334888A (en) * 2001-05-08 2002-11-22 Sanken Electric Co Ltd Semiconductor device and manufacturing method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61219171A (en) * 1985-03-25 1986-09-29 Sanken Electric Co Ltd Multi-cell type transistor
JPH0329299B2 (en) * 1985-03-25 1991-04-23 Sanken Electric Co Ltd
JP2002334888A (en) * 2001-05-08 2002-11-22 Sanken Electric Co Ltd Semiconductor device and manufacturing method therefor

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