JPH0329299B2 - - Google Patents
Info
- Publication number
- JPH0329299B2 JPH0329299B2 JP60060389A JP6038985A JPH0329299B2 JP H0329299 B2 JPH0329299 B2 JP H0329299B2 JP 60060389 A JP60060389 A JP 60060389A JP 6038985 A JP6038985 A JP 6038985A JP H0329299 B2 JPH0329299 B2 JP H0329299B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- wiring conductor
- film
- resistive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 230000000087 stabilizing effect Effects 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 9
- 230000006378 damage Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 208000010392 Bone Fractures Diseases 0.000 description 1
- 206010017076 Fracture Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、焼損し難いエミツタ安定化抵抗を有
するマルチセル型トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-cell transistor having an emitter stabilizing resistor that is difficult to burn out.
大電流化、高速スイツチング化、高周波化とい
つた特性向上の要求に応えるために、マルチエミ
ツタ型あるいはメツシユエミツタ型(ベースアイ
ランド型)といつた多数のセル(小トランジス
タ)が集合したタイプのトランジスタが数多く製
品化されている。
In order to meet the demands for improved characteristics such as larger currents, faster switching, and higher frequencies, there are many types of transistors such as multi-emitter type or mesh emitter type (base island type) that are made up of a large number of cells (small transistors). It has been commercialized.
このマルチセル型トランジスタにおいて、各セ
ルの均一な動作をはかつて二次破壊耐量を向上さ
せるために、各セルのエミツタに直列に抵抗(エ
ミツタ安定化抵抗と呼ばれる)を接続することは
公知である。第14図は、従来のマルチエミツタ
トランジスタの1例を示す一部平面図である。1
はセルを構成する単位エミツタ領域、2はベース
領域である。この単位エミツタ領域1及びベース
領域2の表面には、図では示されていないが、絶
縁膜が形成されている。3はこの絶縁膜に設けら
れたエミツタ接続用開孔、4,5はエミツタ配線
導体、6,7はポリシリコン抵抗膜、8は上記絶
縁膜に設けられたベース接続用開孔、9はベース
配線導体である。この構造では、ポリシリコン抵
抗膜6,7によつて得られる抵抗R1,R2がエミ
ツタ領域1とエミツタ配線導体4との間に接続さ
れた状態となり、エミツタ安定化抵抗として作用
する。エミツタ安定化抵抗の接続構造は種々ある
が、第14図に示すように2つの抵抗膜6,7を
並列接続する構造が適切な抵抗値を得やすく、ま
たパターン設計上も便利であるため多用されてい
る。 In this multi-cell transistor, it is known to connect a resistor (called an emitter stabilizing resistor) in series to the emitter of each cell in order to ensure uniform operation of each cell and to improve secondary breakdown resistance. FIG. 14 is a partial plan view showing an example of a conventional multi-emitter transistor. 1
2 is a unit emitter region constituting a cell, and 2 is a base region. Although not shown in the figure, an insulating film is formed on the surfaces of the unit emitter region 1 and the base region 2. 3 is an opening for emitter connection provided in this insulating film, 4 and 5 are emitter wiring conductors, 6 and 7 are polysilicon resistive films, 8 is an opening for base connection provided in the above insulating film, and 9 is a base. It is a wiring conductor. In this structure, the resistors R 1 and R 2 obtained by the polysilicon resistive films 6 and 7 are connected between the emitter region 1 and the emitter wiring conductor 4, and act as emitter stabilizing resistors. There are various connection structures for the emitter stabilizing resistor, but the structure in which two resistive films 6 and 7 are connected in parallel, as shown in Figure 14, is often used because it is easy to obtain an appropriate resistance value and is convenient for pattern design. has been done.
しかし、L負荷のスイツチング回路等における
逆バイアス二次破壊耐量については、更に改善が
必要であつた。即ち、逆バイアス二次破壊耐量の
試験条件を厳しくして行くと、エミツタ電極のボ
ンデイングバツド(外部接続部)近傍のセルにお
いて、スイツチオフ時に流れる過渡的な電流によ
つて抵抗膜6又は7が焼損し、これ等の抵抗値が
減少し、そのセルに電流が集中して二次破壊に至
るという問題があり、この改善が要望されてい
る。
However, there was a need for further improvement regarding the reverse bias secondary breakdown resistance of L-load switching circuits and the like. That is, when the test conditions for reverse bias secondary breakdown strength are made stricter, the resistance film 6 or 7 is damaged by the transient current flowing during switch-off in the cell near the bonding butt (external connection) of the emitter electrode. There is a problem in that the resistance value of these cells decreases due to burnout, and current concentrates in the cell, leading to secondary destruction, and there is a desire to improve this problem.
そこで本発明の目的は、エミツタ安定化抵抗の
焼損を防止し、もつて逆バイアス二次破壊耐量の
大きいマルチセル型トランジスタを提供すること
にある。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multi-cell transistor that prevents burnout of the emitter stabilizing resistor and has a high reverse bias secondary breakdown resistance.
上記目的を達成するための本発明は、理解を容
易にするために、実施例を示す図面の符号を参照
して説明すると、第1の導電型のコレクタ領域
と、前記コレクタ領域に隣接している第2の導電
型のベース領域と、前記ベース領域に前記コレク
タ領域とは反対側において隣接するように配置さ
れ、且つ複数の島状部分又は網状部分又はストラ
イプ状部分を有している第1の導電型のエミツタ
領域と、前記エミツタ領域及び前記ベース領域の
表面上に設けられている絶縁膜と、前記エミツタ
領域を構成する複数の単位エミツタ領域上の前記
絶縁膜にそれぞれ設けられたエミツタ接続用開孔
と、前記複数の単位エミツタ領域を並列接続する
ためのエミツタ配線導体と、前記ベース領域に接
続されたベース配線導体と、前記単位エミツタ領
域と前記エミツタ配線導体との間に設けられた抵
抗膜とを有するマルチセル型トランジスタにおい
て、前記単位エミツタ領域11aに対応させて第
1及び第2のエミツタ接続用開孔21,22を設
け、前記第1のエミツタ接続用開孔21の中心と
前記第2のエミツタ接続用開孔22の中心とを結
ぶ第1の直線に沿う領域及び前記第1及び第2の
エミツタ接続用開孔21,22間の略中央で前記
第1の直線に直交する第2の直線に沿う領域を有
する略十字状の抵抗膜18,33を設け、前記第
1の直線に沿う領域の抵抗膜の両端部を前記第1
及び第2のエミツタ接続用開孔21,22を通し
て直接に又はエミツタ接続電極16a,16bを
介して前記単位エミツタ領域11aにそれぞれ接
続し、前記第2の直線に沿う領域の抵抗膜の両端
部を前記エミツタ配線導体15a,15bにそれ
ぞれ接続したことを特徴とするマルチセル型トラ
ンジスタに係わるものである。
To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments for ease of understanding. a base region of a second conductivity type, the first base region having a plurality of island-like portions, net-like portions, or stripe-like portions, the base region being arranged adjacent to the base region on the opposite side from the collector region; an emitter region of a conductivity type, an insulating film provided on the surfaces of the emitter region and the base region, and an emitter connection provided on each of the insulating films on a plurality of unit emitter regions constituting the emitter region. an emitter wiring conductor for connecting the plurality of unit emitter areas in parallel, a base wiring conductor connected to the base area, and an emitter wiring conductor provided between the unit emitter area and the emitter wiring conductor. In a multi-cell transistor having a resistive film, first and second emitter connection holes 21 and 22 are provided corresponding to the unit emitter region 11a, and the center of the first emitter connection hole 21 and the A region along the first straight line connecting the center of the second emitter connecting hole 22 and a region perpendicular to the first straight line at approximately the center between the first and second emitter connecting holes 21 and 22. Approximately cross-shaped resistive films 18 and 33 having regions along the second straight line are provided, and both ends of the resistive film in the region along the first straight line are connected to the first straight line.
and connect to the unit emitter region 11a directly through the second emitter connection openings 21 and 22 or via the emitter connection electrodes 16a and 16b, and connect both ends of the resistive film in the region along the second straight line. The present invention relates to a multi-cell transistor characterized in that it is connected to the emitter wiring conductors 15a and 15b, respectively.
本発明の抵抗膜18,33は略十字状に形成さ
れているので、エミツタ配線導体15a,15b
からエミツタ接続用開孔21,22又はエミツタ
接続電極16a,16bまでの抵抗膜18,33
の長さを大きくすることができる。即ち、抵抗膜
18,33のエミツタ接続用開孔21,22を結
ぶ第1の直線に沿つて延びる部分だけ、第14図
及び第6図の従来例に比較して抵抗膜18,33
の長さを長くできる。本発明において従来と同一
の膜厚で同一の抵抗値を得る場合においては、抵
抗膜18,33が長くなつた分だけ抵抗膜18,
33の幅を広くすることができる。この結果、抵
抗膜18,33に於ける電流密度を下げることが
可能になり、抵抗膜18,33が焼損しにくくな
る。
Since the resistive films 18 and 33 of the present invention are formed in a substantially cross shape, the emitter wiring conductors 15a and 15b
Resistive films 18, 33 from to emitter connection openings 21, 22 or emitter connection electrodes 16a, 16b
The length can be increased. That is, only the portion of the resistive films 18, 33 extending along the first straight line connecting the emitter connection openings 21, 22 is smaller than the conventional example shown in FIGS. 14 and 6.
The length of can be increased. In the present invention, when obtaining the same resistance value with the same film thickness as in the past, the resistance film 18, 33 is lengthened by the length of the resistance film 18, 33.
33 can be made wider. As a result, it becomes possible to lower the current density in the resistive films 18 and 33, making it difficult for the resistive films 18 and 33 to burn out.
次に、第1図〜第4図に基づいて本発明の実施
例に係わるマルチエミツタ型シリコントランジス
タについて説明する。第1図は絶縁膜を省略して
トランジスタを示す平面図、第2図は第1図の1
部拡大平面図、第3図は第3図のA−A断面図、
第4図は第2図のB−B断面図である。なお、各
部の区別を明確にするために、第1図及び第2図
の平面図、及び追つて述べる別の実施例におい
て、エミツタ及びベース接続導体15,17に斜
線が付けられている。
Next, a multi-emitter type silicon transistor according to an embodiment of the present invention will be explained based on FIGS. 1 to 4. Figure 1 is a plan view showing the transistor with the insulating film omitted, and Figure 2 is the same as in Figure 1.
3 is a cross-sectional view taken along line A-A in FIG.
FIG. 4 is a sectional view taken along line BB in FIG. In order to clearly distinguish each part, the emitter and base connecting conductors 15 and 17 are shaded in the plan views of FIGS. 1 and 2 and in other embodiments to be described later.
図において、11はN+型(第1の導電型)エ
ミツタ領域、12はP型(第2の導電型)ベース
領域、13はN型高抵抗コレクタ領域、14は低
抵抗コレクタ領域、15a,15bはAl膜から
成る第1及び第2のエミツタ配線導体、16a,
16bはエミツタ接続電極、17aはAl膜から
成るベース配線導体、18はポリシリコン膜から
成るエミツタ安定化抵抗、19はNi膜から成る
コレクタ電極、20はSiO2−Si3N4の2層膜から
成る絶縁膜、21,22,23は絶縁膜20に設
けた開孔である。 In the figure, 11 is an N + type (first conductivity type) emitter region, 12 is a P-type (second conductivity type) base region, 13 is an N-type high resistance collector region, 14 is a low resistance collector region, 15a, 15b is the first and second emitter wiring conductor made of Al film, 16a,
16b is an emitter connection electrode, 17a is a base wiring conductor made of an Al film, 18 is an emitter stabilizing resistor made of a polysilicon film, 19 is a collector electrode made of a Ni film, and 20 is a two-layer film of SiO 2 -Si 3 N 4 The insulating film 21, 22, and 23 are openings provided in the insulating film 20.
エミツタ領域11は島状に配列された多数の単
位エミツタ領域11aを含み、ベース領域12は
チツプ表面においてメツシユ状に配置されてい
る。第1図には単位エミツタ領域11aが12個の
み示されているが、実際にはもつと多く例えば
200個設けられている。 The emitter region 11 includes a large number of unit emitter regions 11a arranged in an island shape, and the base region 12 is arranged in a mesh shape on the chip surface. Although only 12 unit emitter regions 11a are shown in FIG. 1, in reality there may be many, for example.
There are 200 of them.
各単位エミツタ領域11aに対応して第1及び
第2のエミツタ配線導体15a,15bが設けら
れ、更にこれ等を共通に接続する共通接続部15
cが設けられている。第1及び第2のエミツタ配
線導体15a,15bは、絶縁膜20に設けられ
た第1及び第2のエミツタ接続用開孔21,22
を結ぶ第1の直線L1に対して平行であり、且つ
等しい間隔を有する。 First and second emitter wiring conductors 15a and 15b are provided corresponding to each unit emitter region 11a, and a common connection portion 15 that connects these in common
c is provided. The first and second emitter wiring conductors 15a and 15b are connected to the first and second emitter connection openings 21 and 22 provided in the insulating film 20.
It is parallel to the first straight line L 1 connecting the lines and has equal intervals.
ベース配線導体17aは、エミツタ配線導体1
5a,15bに平行に延びるように設けられ、絶
縁膜20に設けられたベース接続用開孔23を介
してベース領域12に接続されている。なお、各
ベース配線導体17aは共通接続部分17bに接
続されている。また、開孔23は、単位エミツタ
領域11aの角に対応して設けられている。 The base wiring conductor 17a is the emitter wiring conductor 1
5a and 15b, and is connected to the base region 12 via a base connection opening 23 provided in the insulating film 20. Note that each base wiring conductor 17a is connected to a common connection portion 17b. Further, the openings 23 are provided corresponding to the corners of the unit emitter regions 11a.
エミツタ安定化抵抗膜18は略十字状に形成さ
れ、第1及び第2の開孔21,22のエミツタ接
続電極16a,16bに接続されていると共に、
第1及び第2のエミツタ配線導体15a,15b
に接続されている。第1及び第2の開孔21,2
2は単位エミツタ領域11aの一方の方向におけ
る二等分線に対応する第1の直線L1上に設けら
れ、且つ他方の方向における二等分線に対応する
第2の直線L2から等しい距離上に設けられてい
る。なお、第2の直線L2は第1の直線L1に直交
し、第1の開孔21と第2の開孔22との間の中
央を通つている。エミツタ安定化抵抗膜18は、
第1及び第2の直線L1,L2を中心に対称に形成
されている。このエミツタ安定化抵抗膜18の第
1の直線L1に沿う領域の一端部18aは第1の
エミツタ接続電極16aに接続され、他端部18
bは第2のエミツタ接続電極16bに接続され、
第2の直線L2に沿う領域の一端部18cは第1
のエミツタ配線導体15aに接続され、他端部1
8dは第2のエミツタ配線導体15bに接続され
ている。 The emitter stabilizing resistive film 18 is formed in a substantially cross shape, and is connected to the emitter connecting electrodes 16a, 16b of the first and second openings 21, 22.
First and second emitter wiring conductors 15a, 15b
It is connected to the. First and second openings 21, 2
2 is provided on the first straight line L1 corresponding to the bisector of the unit emitter area 11a in one direction, and at an equal distance from the second straight line L2 corresponding to the bisector in the other direction. is placed above. Note that the second straight line L 2 is perpendicular to the first straight line L 1 and passes through the center between the first aperture 21 and the second aperture 22 . The emitter stabilizing resistive film 18 is
It is formed symmetrically about the first and second straight lines L 1 and L 2 . One end 18a of the emitter stabilizing resistive film 18 along the first straight line L1 is connected to the first emitter connecting electrode 16a, and the other end 18a is connected to the first emitter connecting electrode 16a.
b is connected to the second emitter connection electrode 16b,
One end 18c of the area along the second straight line L2 is the first
is connected to the emitter wiring conductor 15a of the other end 1.
8d is connected to the second emitter wiring conductor 15b.
上述の如く構成されたトランジスタに第5図に
示す如き波形24のベース電流を流してスイツチ
ング動作させ、二次破壊させるコレクタ電流IS/B
(平均化された値)を求めた。この際、コレク
タ・エミツタ間にダイオードクランプの方法によ
つて800Vの電圧を印加し、負荷としてL=
2.8mHのコイルを接続し、第5図の正方向ベー
ス電流IB1を2.5Aに固定し、この正方向ベース電
流IB1のパルス幅Wを変えることによつてコレク
タ電流ICを変化させて破壊に至るコレクタ電流
IS/Bの値を測定した。なお、逆方向のベース電流
IB2の値を−1.0A、−2.0A、−3.0Aの3段階に変化
させ、それぞれのIS/Bを求めた。 A base current having a waveform 24 as shown in FIG. 5 is caused to flow through the transistor configured as described above to cause a switching operation, and the collector current I S/B is caused to cause secondary destruction.
(averaged value) was calculated. At this time, a voltage of 800V was applied between the collector and emitter using a diode clamp method, and L=
Connect a 2.8 mH coil, fix the positive direction base current I B1 in Figure 5 to 2.5 A, and change the collector current I C by changing the pulse width W of this positive direction base current I B1 . Collector current leading to destruction
The value of I S/B was measured. In addition, the base current in the reverse direction
The value of I B2 was varied in three steps: -1.0A, -2.0A, and -3.0A, and each I S/B was determined.
この結果、IB2=−1.0Aの時のIS/Bは12A、 IB2=−2.0Aの時のIS/Bは11A、 IB2=−0.3Aの時のIS/Bは10Aであつた。As a result, I S/B is 12 A when I B2 = -1.0 A, I S/B is 11 A when I B2 = -2.0 A, and I S/B is 10 A when I B2 = -0.3 A. It was hot.
比較のために、抵抗膜18を設けない他は第1
の実施例と同一にしてIS/Bを測定したところ、IB2
=−1.0Aの時のIS/Bは2Aであり、IB2=−2.0A及び
IB2=−3.0Aの時のIS/Bは2A未満であつた。また、
抵抗値は第1の実施例の抵抗膜18と同一である
が、パターンを第14図に示す抵抗膜6,7と
し、その他は第1の実施例と同一にしてIS/Bを測
定したところ、
IB2=−1.0Aの時のIS/Bは7A、
IB2=−2.0Aの時のIS/Bは2A、
IB2=−3.0Aの時のIS/Bは2Aであつた。 For comparison, the first example except that the resistive film 18 is not provided
When I S/B was measured in the same manner as in the example, I B2
I S/B when = -1.0A is 2A, I B2 = -2.0A and
I S/B was less than 2 A when I B2 = -3.0 A. Also,
The resistance value was the same as that of the resistive film 18 of the first example, but the pattern was changed to the resistive films 6 and 7 shown in FIG. However, when I B2 = -1.0A, I S/B is 7A, when I B2 = -2.0A, I S/B is 2A, and when I B2 = -3.0A, I S/B is 2A. It was hot.
この測定結果から明らかな如く、IB2=−1.0A
の時にすでに二次破壊耐量の改善効果が現われ、
IB2=−2.0Aの時には大幅に改善される。この改
善効果は、第7図で矢印29,30,31,32
で示すエミツタ接続用開孔21,22とエミツタ
配線導体15a,15bとの間の電流通路の長さ
即ち抵抗膜18の長さが長くなり、従来と同一の
抵抗値を得る場合には抵抗膜18の幅又は厚みを
大きくすることが可能に成り、ここでの電流密度
が低くなることに基いて生じる。また、抵抗膜1
8を十字状にすれば、E、Fで示す中心領域の電
流密度が低くなり、この中心領域での焼損が生じ
ない。 As is clear from this measurement result, I B2 = −1.0A
The effect of improving secondary fracture resistance was already visible at the time of
Significant improvement is achieved when I B2 = -2.0A. This improvement effect can be seen at arrows 29, 30, 31, and 32 in Figure 7.
The length of the current path between the emitter connection openings 21, 22 and the emitter wiring conductors 15a, 15b, that is, the length of the resistive film 18, becomes longer, and in order to obtain the same resistance value as before, the resistive film It becomes possible to increase the width or thickness of 18, which results from the lower current density there. In addition, the resistive film 1
If 8 is made into a cross shape, the current density in the central regions indicated by E and F will be low, and no burnout will occur in these central regions.
次に、第8図〜第11図に示す第2の実施例に
係わるトランジスタを説明する。但し、この第2
の実施例の図面、及び後で述べる第12図、第1
3図、及び第15図において第1図〜第4図と共
通する部分には同一の符号を付してその説明を省
略する。 Next, a transistor according to a second embodiment shown in FIGS. 8 to 11 will be explained. However, this second
12 and 1 which will be described later.
In FIGS. 3 and 15, parts common to those in FIGS. 1 to 4 are designated by the same reference numerals, and their explanations will be omitted.
この第2の実施例では、第1図〜第4図のポリ
シリコン膜のエミツタ安定化抵抗膜18の代り
に、Al膜から成るエミツタ安定化抵抗膜33が
設けられている。この抵抗膜33は、エミツタ配
線導体15a,15b、エミツタ接続電極16
a,16bと同じ材料Alであるが、幅及び/又
は厚みを小さくし、断面積を小さくすることによ
つて所望の抵抗値が得られるように形成されてい
る。例えば、エミツタ配線導体15a,15bの
幅が30μm、厚さが5μmであるのに対して、抵抗
膜33の幅は30μm、厚さが1μmである。第8図
〜第11図のトランジスタは、抵抗膜24の材料
を変えた点を除いて第1図〜第4図のトランジス
タと同一に構成されている。 In this second embodiment, an emitter stabilizing resistor film 33 made of an Al film is provided in place of the emitter stabilizing resistor film 18 made of a polysilicon film in FIGS. 1 to 4. This resistive film 33 includes emitter wiring conductors 15a, 15b, emitter connection electrode 16
Although it is made of the same material Al as a and 16b, it is formed so that a desired resistance value can be obtained by reducing the width and/or thickness and reducing the cross-sectional area. For example, while the emitter wiring conductors 15a and 15b have a width of 30 μm and a thickness of 5 μm, the resistive film 33 has a width of 30 μm and a thickness of 1 μm. The transistors shown in FIGS. 8 to 11 have the same structure as the transistors shown in FIGS. 1 to 4, except that the material of the resistive film 24 is changed.
第2の実施例のトランジスタの二次破壊に至る
コレクタ電流IS/Bを第1の実施例と同一方法で測
定したところ、
IB2=−1.0Aの時のIS/Bは6A、
IB2=−2.0Aの時のIS/Bは5A、
IB2=−3.0Aの時のIS/Bは5Aであつた。 When the collector current I S/B leading to secondary breakdown of the transistor in the second embodiment was measured using the same method as in the first embodiment, I S/B was 6 A when I B2 = -1.0 A, and I When B2 = -2.0A, I S/B was 5A, and when I B2 = -3.0A, I S/B was 5A.
この結果から明らかな如く、IB2が大きい時、
即ち深い逆バイアス時において二次破壊耐量の向
上が認められた。第2の実施例においては、エミ
ツタ安定化抵抗膜33の抵抗値が、第14図の従
来の抵抗6,7の抵抗値よりも小さく、エミツタ
安定化に対して不利な値であるにも拘らず、深い
逆バイアス時に二時破壊耐量が向上するのは、抵
抗膜33を十字状に形成したためである。なお、
このAl膜を抵抗膜33とする場合には、焼損に
よつてエミツタがオープン状態になり、他のセル
の負担が増大し、破壊に至る。 As is clear from this result, when I B2 is large,
That is, an improvement in secondary breakdown resistance was observed during deep reverse bias. In the second embodiment, although the resistance value of the emitter stabilizing resistive film 33 is smaller than the resistance value of the conventional resistors 6 and 7 shown in FIG. 14, which is a disadvantageous value for emitter stabilization, First, the reason why the instantaneous breakdown resistance is improved during deep reverse bias is that the resistive film 33 is formed in a cross shape. In addition,
When this Al film is used as the resistive film 33, the emitter becomes open due to burnout, increasing the burden on other cells and leading to destruction.
本実施例の如く、抵抗膜33をエミツタ配線導
体15a,15b等と同一材料とすれば、製造工
程が簡略化され、コストダウンが可能になる。な
お、第14図の構造の抵抗6,7をこの第2の実
施例と同様にAl膜で構成しようとすると、実用
的長さの範囲で必要な抵抗値を得ることが困難で
あり、例え必要な抵抗値が得られても、二次破壊
が起こり易い。 If the resistive film 33 is made of the same material as the emitter wiring conductors 15a, 15b, etc. as in this embodiment, the manufacturing process can be simplified and costs can be reduced. Note that if it is attempted to construct the resistors 6 and 7 of the structure shown in FIG. 14 using Al films as in the second embodiment, it will be difficult to obtain the necessary resistance value within a practical length range. Even if the required resistance value is obtained, secondary destruction is likely to occur.
本発明は、上述の実施例に限定されるものでな
く、例えば次の変形例が可能なものである。
The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.
(A) 第12図及び第13図に示す如く、ベース領
域12を島状に配置し、エミツタ領域11をメ
ツシユ状に配置したメツシユエミツタ型トラン
ジスタ(ペースアイランド型トランジスタ)に
も本発明を適用することが可能である。この場
合には、単位エミツタ領域11aに対応させて
第1及び第2の開孔21,22を設け、これと
第1及び第2のエミツタ配線導体15a,15
bとの間に第12図に示す如く第1の実施例と
同一のポリシリコン膜の抵抗膜18を設ける
か、又は第13図に示す如く第2の実施例と同
一のAl膜の抵抗膜33を設ける。これにより、
第1及び第2の実施例と全く同様な作用効果が
得られる。(A) As shown in FIGS. 12 and 13, the present invention can also be applied to a mesh emitter type transistor (pace island type transistor) in which the base region 12 is arranged in an island shape and the emitter region 11 is arranged in a mesh shape. is possible. In this case, first and second openings 21 and 22 are provided corresponding to the unit emitter region 11a, and the first and second emitter wiring conductors 15a and 15 are connected to each other.
A resistive film 18 made of the same polysilicon film as in the first embodiment is provided as shown in FIG. 12, or a resistive film 18 made of the same Al film as in the second embodiment is provided as shown in FIG. 33 will be provided. This results in
Exactly the same effects as in the first and second embodiments can be obtained.
(B) 第15図に示す如く、メツシユエミツタ型ト
ランジスタにおいて、エミツタ接続用開孔2
1,22を規則正しく繰返して配置し、開孔2
1,22のそれぞれの間に十字状のポリシリコ
ン膜から成る抵抗膜18又はAl膜から成る抵
抗膜を設けてもよい。この場合には、開孔2
1,22が隣接する単位エミツタ領域11aと
兼用される。(B) As shown in Figure 15, in a mesh emitter type transistor, the emitter connection opening 2
1 and 22 are regularly arranged repeatedly, and the opening 2 is
A resistive film 18 made of a cross-shaped polysilicon film or a resistive film made of an Al film may be provided between each of 1 and 22. In this case, the opening 2
1 and 22 are also used as adjacent unit emitter regions 11a.
(C) 抵抗膜18,33をポリシリコン、Al以外
の抵抗材料又は金属材料で形成してもよい。要
するに、抵抗膜18,33は、抵抗が得られる
膜であれば、どの様な材料でもよい。(C) The resistive films 18 and 33 may be formed of polysilicon, a resistive material other than Al, or a metal material. In short, the resistive films 18 and 33 may be made of any material as long as it provides resistance.
(D) 抵抗膜18,33のパターンを正確な十字状
とせず、交差部分に曲率をつけた形状としても
よい。また、抵抗膜18,24の第1の直線
L1に沿う部分の長さを、第2の直線L2に沿う
部分の幅に近づけるか、又は等しくするように
パターンを変形してもよい。(D) The patterns of the resistive films 18 and 33 may not be exactly cross-shaped, but may have a curvature at the intersection. In addition, the first straight line of the resistive films 18 and 24
The pattern may be modified so that the length of the portion along L 1 approaches or becomes equal to the width of the portion along the second straight line L 2 .
(E) 抵抗膜18,33を開孔21,22の中にも
設け、エミツタ領域11に直接に接続するよう
にしてもよい。(E) The resistive films 18 and 33 may also be provided in the openings 21 and 22 and connected directly to the emitter region 11.
上述から明らかな如く、本発明に従つて、一対
の開孔を結ぶ第1の直線に沿つて抵抗膜を設ける
と共に、第1の直線に直交する第2の直線に沿つ
ても抵抗膜を設け、この第2の直線に沿う抵抗膜
の両端をエミツタ配線導体に接続すれば、抵抗膜
が焼損し難くなり、二次破壊耐量が向上する。
As is clear from the above, according to the present invention, a resistive film is provided along the first straight line connecting the pair of openings, and a resistive film is also provided along the second straight line orthogonal to the first straight line. If both ends of the resistive film along this second straight line are connected to the emitter wiring conductor, the resistive film is less likely to be burnt out and the secondary breakdown resistance is improved.
第1図は本発明の第1の実施例のトランジスタ
を示す平面図、第2図は第1図の一部拡大平面
図、第3図は第2図のA−A線断面図、第4図は
第2図のB−B線断面図、第5図は二次破壊コレ
クタ電流を測定するための電流波形図、第6図は
従来のエミツタ安定化抵抗を示す平面図、第7図
は本発明のエミツタ安定化抵抗膜における電流の
流れ方を示す平面図、第8図は本発明の第2の実
施例のトランジスタを示す平面図、第9図は第8
図の一部拡大平面図、第10図は第9図のA−A
線断面図、第11図は第9図のB−B線断面図、
第12図及び第13図は変形例のトランジスタを
示す平面図、第14図は従来のトランジスタの一
部を示す平面図、第15図は変形例のトランジス
タの一部を示す平面図である。
11…エミツタ領域、11a…単位エミツタ領
域、12…ベース領域、13…コレクタ領域、1
5a,15b…エミツタ配線導体、18…エミツ
タ安定化抵抗膜、20…絶縁膜、21,22…開
孔。
1 is a plan view showing a transistor according to a first embodiment of the present invention, FIG. 2 is a partially enlarged plan view of FIG. 1, FIG. 3 is a sectional view taken along line A-A in FIG. The figure is a sectional view taken along the line B-B in Figure 2, Figure 5 is a current waveform diagram for measuring the secondary breakdown collector current, Figure 6 is a plan view showing a conventional emitter stabilizing resistor, and Figure 7 is a A plan view showing how current flows in the emitter stabilizing resistor film of the present invention, FIG. 8 is a plan view showing the transistor of the second embodiment of the present invention, and FIG.
A partially enlarged plan view of the figure, Figure 10 is A-A of Figure 9.
A line sectional view, FIG. 11 is a BB line sectional view of FIG. 9,
12 and 13 are plan views showing a transistor of a modified example, FIG. 14 is a plan view showing a part of a conventional transistor, and FIG. 15 is a plan view showing a part of a transistor of a modified example. DESCRIPTION OF SYMBOLS 11... Emitter area, 11a... Unit emitter area, 12... Base area, 13... Collector area, 1
5a, 15b... Emitter wiring conductor, 18... Emitter stabilizing resistance film, 20... Insulating film, 21, 22... Opening.
Claims (1)
のベース領域と、 前記ベース領域に前記コレクタ領域とは反対側
において隣接するように配置され、且つ複数の島
状部分又は網状部分又はストライプ状部分を有し
ている第1の導電型のエミツタ領域と、 前記エミツタ領域及び前記ベース領域の表面上
に設けられている絶縁膜と、 前記エミツタ領域を構成する複数の単位エミツ
タ領域上の前記絶縁膜にそれぞれ設けられたエミ
ツタ接続用開孔と、 前記複数の単位エミツタ領域を並列接続するた
めのエミツタ配線導体と、 前記ベース領域に接続されたベース配線導体
と、 前記単位エミツタ領域と前記エミツタ配線導体
との間に設けられた抵抗膜と を有するマルチセル型トランジスタにおいて、 前記単位エミツタ領域11aに対応させて第1
及び第2のエミツタ接続用開孔21,22を設
け、前記第1のエミツタ接続用開孔21の中心と
前記第2のエミツタ接続用開孔22の中心とを結
ぶ第1の直線に沿う領域及び前記第1及び第2の
エミツタ接続用開孔21,22間の略中央で前記
第1の直線に直交する第2の直線に沿う領域を有
する略十字状の抵抗膜18,33を設け、前記第
1の直線に沿う領域の抵抗膜の両端部を前記第1
及び第2のエミツタ接続用開孔21,22を通し
て直接に又はエミツタ接続電極16a,16bを
介して前記単位エミツタ領域11aにそれぞれ接
続し、前記第2の直線に沿う領域の抵抗膜の両端
部を前記エミツタ配線導体15a,15bにそれ
ぞれ接続したことを特徴とするマルチセル型トラ
ンジスタ。 2 前記抵抗膜は、前記エミツタ配線導体15
a,15bと異なる材料から成るものである特許
請求の範囲第1項記載のマルチセル型トランジス
タ。 3 前記抵抗膜がポリシリコン膜である特許請求
の範囲第2項記載のマルチセル型トランジスタ。 4 前記抵抗膜が前記エミツタ配線導体15a,
15bと同じ材料から成り、その断面積が前記エ
ミツタ配線導体15a,15bのそれよりも小さ
くされたものである特許請求の範囲第1項記載の
マルチセル型トランジスタ。 5 前記抵抗膜及び前記エミツタ配線導体が共に
Al膜である特許請求の範囲第4項記載のマルチ
セル型トランジスタ。[Scope of Claims] 1: a collector region of a first conductivity type; a base region of a second conductivity type adjacent to the collector region; and a base region adjacent to the base region on a side opposite to the collector region; an emitter region of a first conductivity type, which is disposed on the surface of the emitter region and has a plurality of island-like portions, net-like portions, or stripe-like portions; an insulating film provided on the surfaces of the emitter region and the base region; , emitter connection openings provided in the insulating film on the plurality of unit emitter regions constituting the emitter region; an emitter wiring conductor for connecting the plurality of unit emitter regions in parallel; and an emitter wiring conductor in the base region. In a multi-cell transistor having a connected base wiring conductor and a resistive film provided between the unit emitter region and the emitter wiring conductor, a first base wiring conductor corresponding to the unit emitter region 11a is provided.
and a region along a first straight line connecting the center of the first emitter connecting hole 21 and the center of the second emitter connecting hole 22; and a substantially cross-shaped resistive film 18, 33 having a region extending along a second straight line orthogonal to the first straight line approximately in the center between the first and second emitter connection openings 21, 22; Both ends of the resistive film in the region along the first straight line are
and connect to the unit emitter region 11a directly through the second emitter connection openings 21 and 22 or via the emitter connection electrodes 16a and 16b, and connect both ends of the resistive film in the region along the second straight line. A multi-cell transistor characterized in that it is connected to the emitter wiring conductors 15a and 15b, respectively. 2 The resistive film is connected to the emitter wiring conductor 15.
The multi-cell transistor according to claim 1, wherein the transistors a and 15b are made of different materials. 3. The multi-cell transistor according to claim 2, wherein the resistive film is a polysilicon film. 4. The resistive film is connected to the emitter wiring conductor 15a,
2. The multi-cell transistor according to claim 1, which is made of the same material as said emitter wiring conductor 15b and whose cross-sectional area is smaller than that of said emitter wiring conductor 15a, 15b. 5 The resistive film and the emitter wiring conductor are both
The multi-cell transistor according to claim 4, which is an Al film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6038985A JPS61219171A (en) | 1985-03-25 | 1985-03-25 | Multi-cell type transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6038985A JPS61219171A (en) | 1985-03-25 | 1985-03-25 | Multi-cell type transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61219171A JPS61219171A (en) | 1986-09-29 |
JPH0329299B2 true JPH0329299B2 (en) | 1991-04-23 |
Family
ID=13140740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6038985A Granted JPS61219171A (en) | 1985-03-25 | 1985-03-25 | Multi-cell type transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61219171A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63211673A (en) * | 1987-02-26 | 1988-09-02 | Shindengen Electric Mfg Co Ltd | Power transistor |
JP4934905B2 (en) * | 2001-05-08 | 2012-05-23 | サンケン電気株式会社 | Semiconductor device and manufacturing method thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5516427A (en) * | 1978-07-21 | 1980-02-05 | Toshiba Corp | Method of manufacturing semiconductor device |
-
1985
- 1985-03-25 JP JP6038985A patent/JPS61219171A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5516427A (en) * | 1978-07-21 | 1980-02-05 | Toshiba Corp | Method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS61219171A (en) | 1986-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6331466B1 (en) | Insulated gate semiconductor device and manufacturing method thereof | |
US20130009206A1 (en) | Semiconductor device | |
US4833513A (en) | MOS FET semiconductor device having a cell pattern arrangement for optimizing channel width | |
JPS60187072A (en) | Hall element | |
US6140680A (en) | Integrated power semiconductor transistor with current sensing | |
JPH0329299B2 (en) | ||
US4500900A (en) | Emitter ballast resistor configuration | |
EP0239960B1 (en) | Power transistor device | |
US5844285A (en) | Body contact structure for semiconductor device | |
JP2940399B2 (en) | Semiconductor device | |
JP2536302B2 (en) | Insulated gate type bipolar transistor | |
US4717886A (en) | Operational amplifier utilizing resistors trimmed by metal migration | |
US5010383A (en) | Power transistor device and method for making the same | |
US5204735A (en) | High-frequency semiconductor device having emitter stabilizing resistor and method of manufacturing the same | |
US4757368A (en) | Semiconductor device having electric contacts with precise resistance values | |
JPH0442919Y2 (en) | ||
US5341020A (en) | Integrated multicellular transistor chip for power switching applications | |
JP3253468B2 (en) | Semiconductor device | |
KR920007784B1 (en) | High feequency semiconductor with emitter stabilized resistor and its manufacturing method | |
JP2524553Y2 (en) | Power semiconductor device | |
US6198379B1 (en) | Semiconductor component with piezoresistive measuring shunts | |
JPH0691247B2 (en) | Bidirectional semiconductor device | |
KR100302195B1 (en) | Triac device | |
JP2000294765A (en) | Semiconductor controlled rectifying device | |
JP2619907B2 (en) | Bidirectional semiconductor switching device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |