JPS61219171A - Multi-cell type transistor - Google Patents

Multi-cell type transistor

Info

Publication number
JPS61219171A
JPS61219171A JP6038985A JP6038985A JPS61219171A JP S61219171 A JPS61219171 A JP S61219171A JP 6038985 A JP6038985 A JP 6038985A JP 6038985 A JP6038985 A JP 6038985A JP S61219171 A JPS61219171 A JP S61219171A
Authority
JP
Japan
Prior art keywords
emitter
region
straight line
resistive film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6038985A
Other languages
Japanese (ja)
Other versions
JPH0329299B2 (en
Inventor
Masaru Yoneda
米田 勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP6038985A priority Critical patent/JPS61219171A/en
Publication of JPS61219171A publication Critical patent/JPS61219171A/en
Publication of JPH0329299B2 publication Critical patent/JPH0329299B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To improve the secondary breakdown voltage by a method wherein resistance films are formed along the first straight line connecting a pair of openings to each other and then the resistance films are also formed along the second straight line orthogonal to the first straight line while both ends of resistance films along the second straight line are connected to emitter wiring conductors. CONSTITUTION:An emitter stabilizing resistance films 18 almost crosswise formed are connected to emitter connecting electrodes 16a, 16b of the first and the second openings 21, 22 simultaneously to the first and the second emitter wiring conductors 15a, 15b. The first and the second openings 21, 22 are provided on the first straight line L1 corresponding to a bisector in one direction of unit emitter regions 11a as well as on the positions equidistant from the second straight line L2 corresponding to another bisector in the other direction. The second straight line L2 orthogonal to the first straight line L1 passes through the central part between the first and the second openings 21 and 22. The emitter stabilizing resistance films 18 are symmetrically formed centering on the first and the second straight lines L1 and L2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、焼損し難いエミッタ安定化抵抗ン有スルマル
チセル型トランジスタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-cell transistor with an emitter stabilizing resistor that is not easily burnt out.

〔従来の技術〕[Conventional technology]

大電流化、高速スイッチング化、高周波化といった%性
向上の要求に応えるために、マルチエミッタ型あるいは
メツシュエミッタ型(ベースアイランド型)といった多
数のセル(小トランジスタ]が集合したタイプのトラン
ジスタが数多く製品化されている。
In order to meet the demands for improved efficiency such as larger currents, faster switching, and higher frequencies, there are many types of transistors that are made up of a large number of cells (small transistors), such as multi-emitter type or mesh emitter type (base island type). It has been commercialized.

このマルチセル型トランジスタにおいて、各セルの均一
な動作χはかつて二次破壊耐量χ向上させるために、各
セルのエミッタに直列に抵抗(エミッタ安定化抵抗と呼
ばれる]ン接続することは公矧である。第14図は、従
来のマルチエミッタトランジスタの1例乞示す一部平面
図である。(1)はセルン構成する単位エミッタ領域、
(2)はベース領域である。この単位エミッタ領域(1
)及びベース領域(2)の表面には1図では示されてい
ないが、絶縁膜が形成されている。(3)はこの絶縁膜
に設けられたエミッタ接続用開孔、 (4)(51はエ
ミッタ配線置体、 (6)<7>はポリシリコン抵抗膜
、(8)は上記絶縁膜に設けられたベース接続用開孔、
(9)はベース配線導体である。この構造では、ポリシ
リコン抵抗膜(6) (7)によって得られる抵抗Rt
 、 Rtがエミッタ領域(1)とエミッタ配線導体(
4)との間に接続された状態となり、エミッタ安定化抵
抗として作用する。エミッタ安定化抵抗の接続構造は種
々あるが、第14図に示すように2つの抵抗膜(61(
7) ’2並列接続する構造が適切な抵抗値ン得やす(
、またパターン設計上も便利であるため多用されている
In this multi-cell transistor, it is common practice to connect a resistor (called an emitter stabilizing resistor) in series to the emitter of each cell in order to improve the secondary breakdown resistance χ. 14 is a partial plan view showing an example of a conventional multi-emitter transistor. (1) shows a unit emitter region constituting a cell;
(2) is the base area. This unit emitter area (1
Although not shown in FIG. 1, an insulating film is formed on the surfaces of the base region (2) and the base region (2). (3) is an opening for emitter connection provided in this insulating film, (4) (51 is an emitter wiring arrangement body, (6) <7> is a polysilicon resistive film, and (8) is an opening provided in the above insulating film. hole for base connection,
(9) is a base wiring conductor. In this structure, the resistance Rt obtained by the polysilicon resistance films (6) (7)
, Rt is the emitter region (1) and the emitter wiring conductor (
4) and acts as an emitter stabilizing resistor. There are various connection structures for emitter stabilizing resistors, but as shown in Fig. 14, two resistive films (61 (
7) It is easier to obtain an appropriate resistance value by connecting two in parallel.
, is also frequently used because it is convenient for pattern design.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、L負荷のスイッチング回路等における逆バイア
ス二次破壊耐量については、更に改善が必要であった。
However, further improvement was required regarding the reverse bias secondary breakdown resistance of L-load switching circuits and the like.

即ち、逆バイアス二次破壊耐量の試験条件を厳しくして
行くと、エミッタ電衡のポンディングパッド(外部接続
部)近傍のセルにおいて、スイッチオフ時に流れる過渡
的な電流によって抵抗膜(6)又は(7)が焼損し、こ
れ等の抵抗値が減少し、そのセルに電流が集中して二次
破壊に至るという問題があり、この改善が要望されてい
る。
In other words, when the test conditions for reverse bias secondary breakdown strength are made stricter, the resistance film (6) or There is a problem in that (7) is burned out, the resistance value of these cells decreases, and current is concentrated in the cell, leading to secondary destruction, and an improvement is desired.

そこで本発明の目的は、エミッタ安定化抵抗の焼損ケ防
止し、もって逆バイアス二次破壊耐量の大きいマルチセ
ル型トランジスタビ提供することにある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multi-cell type transistor which prevents burnout of the emitter stabilizing resistor and has a high reverse bias secondary breakdown resistance.

〔間萌点χ解決するための手段〕[Means for solving the problem]

上記目的ケ運成するための本発明は、理解を容易にする
ために、実施例を示す図面の符号ン参照して説明すると
、第1の導電型のコレクタ領域と。
In order to facilitate understanding, the present invention for achieving the above objects will be described with reference to the reference numerals in the drawings showing the embodiments.

前記コレクタ領域罠隣接している第2の導電型のベース
領域と、前記ベース領域に前記コレクタ領域とは反対側
において隣接するように配置され。
The collector region trap is arranged to be adjacent to an adjacent base region of a second conductivity type, and to be adjacent to the base region on a side opposite to the collector region.

且つ複数の島状部分又は網状部分又はストライプ状部分
り有している第1の導電型のエミッタ領域と、前記エミ
ッタ領域及び前記ベース領域の表面上に設けられている
?3縁膜と、前記エミッタ領域を構成する複数の単位エ
ミッタ領域上の前記絶縁膜にそれぞれ設けられたエミッ
タ接続用開孔と、前記複数の単位エミッタ領域ケ並列接
続するためのエミッタ配線導体と、前記ベース領域に接
続されたベース配線導体と、前記単位エミッタ領域と前
記エミッタ配線導体との間に設けられた抵抗膜とを有す
るマルチセル型トランジスタにおいて。
and a first conductivity type emitter region having a plurality of island-like portions, net-like portions, or stripe-like portions, and a first conductivity type emitter region provided on the surfaces of the emitter region and the base region. three edge films, emitter connection openings provided in the insulating film on the plurality of unit emitter regions constituting the emitter region, and emitter wiring conductors for connecting the plurality of unit emitter regions in parallel; A multi-cell transistor comprising a base wiring conductor connected to the base region, and a resistive film provided between the unit emitter region and the emitter wiring conductor.

前記単位エミッタ領域(11a)に対応させて第1及び
第2のエミッタ接続用開孔(211のを設け、#記第1
のエミッタ接続用開孔(21)(22Jの中心と前記第
2のエミッタ接続用開孔のの中心とを結ぶ第1の直線に
沿う領域及び前記第1及び第2のエミッタ接続用開孔(
2D(221間の略中央で前記第1の直線に直交するI
@20直線に沿う領域に抵抗膜(111gロン設け、前
記第1のil線に沿う領域の抵抗膜の両端部を前記第1
及び第2のエミッタ接続用開孔(211+221 y!
−通して厘接忙又はエミッタ接続を極(16a)<16
b)’を介して前記単位エミッタ領域(11a)にそれ
ぞれ接続し、前記第2の直線に沿う領域の抵抗膜の両端
部を前記エミッタ配線導体(15aJ(15bJにそれ
ぞれ接続したことケ特徴とするマルチセル型トランジス
タに係わるものである。
First and second emitter connection openings (211) are provided corresponding to the unit emitter region (11a), and the first
The area along the first straight line connecting the center of the emitter connection hole (21) (22J and the center of the second emitter connection hole) and the first and second emitter connection hole (21)
2D (I perpendicular to the first straight line at approximately the center between 221
@20 A resistive film (111 g long) is provided in the region along the straight line, and both ends of the resistive film in the region along the first IL line are
and second emitter connection hole (211+221 y!
- connect the terminal or emitter through the pole (16a) <16
b)' are respectively connected to the unit emitter region (11a), and both ends of the resistive film in the region along the second straight line are respectively connected to the emitter wiring conductor (15aJ (15bJ). This relates to multi-cell transistors.

〔作 用〕[For production]

上記発明の抵抗膜(181關における動作ケ、第14図
に示す従来の抵抗膜(6ン(7)における動作と比較し
て説明する。第6図は第14図の抵抗膜(6)、(7)
における電流の流れを示すものである。この抵抗膜(6
)(7)の焼損状態から推察して、抵抗M(6)(7)
にスイッチオフ時に流れる過渡的な電流の通路は矢E!
J(251@@@に示す如く中央部(00でしほられた
状態に偏位していると考えられる。この結果、中央部(
0■]の電流密度が許容値ン越え、ここが焼損し、抵抗
値が減少し、この抵抗膜(6) (7)が接続されてい
る単位エミッタ領域(セル)に電流が集中し、二次破壊
に至る。−万、本発明に従う、第7図の抵Fc膜賭にお
いては、単位エミッタ領域における2つのエミッタ接続
用開孔(21)のからエミッタ配線導体(15a)(1
5b)に流れる電流の通路は矢l:l] 09 C3G
 311 (321に示すように大別される。エミッタ
に接続される抵抗膜α〜の一対の端B’B(18a)(
18b)から流れ出た電流は、第6図の場合と同様に中
央部■[F]に偏位しようとするが、流れの方向が強制
的に直角方向に曲げられ、エミッタ配線導体(151)
(151))に向って流れる。この結果、を流集中が防
止され、抵抗膜α&の焼損が起き難く、逆バイアスに基
づ(二次破壊が少なくなる。
The operation of the resistive film (181) of the above invention will be explained in comparison with the operation of the conventional resistive film (6) shown in FIG. 14. (7)
This shows the flow of current at . This resistive film (6
)(7), the resistance M(6)(7)
The path of the transient current that flows when the switch is turned off is arrow E!
As shown in J(251@@@, it is thought that the central part (
0■] exceeds the allowable value, the area burns out, the resistance value decreases, and the current concentrates in the unit emitter region (cell) to which this resistive film (6) (7) is connected, resulting in The next step is destruction. - In the resistor Fc film according to the present invention shown in FIG. 7, the emitter wiring conductor (15a) (1
The path of the current flowing in 5b) is arrow l:l] 09 C3G
311 (roughly divided as shown in 321. A pair of ends B'B (18a) of the resistive film α connected to the emitter
The current flowing out from the emitter wiring conductor (151) tries to deviate to the central part ■[F] as in the case of Fig. 6, but the direction of flow is forcibly bent to the right angle direction.
(151)). As a result, current flow is prevented, burnout of the resistive film α& is less likely to occur, and secondary damage due to reverse bias is reduced.

〔実施例〕〔Example〕

次に、第1囚〜第4図に基づいて本発明の実施例に係わ
るマルチエミッタ型シリコントランジスタについて説明
する。第1図は絶縁膜を省略してトランジスタを示す平
面囚、第2図は第1因の1部拡大平面図、第3図は第3
図のA−A断面図。
Next, a multi-emitter type silicon transistor according to an embodiment of the present invention will be described based on FIGS. 1 to 4. Figure 1 is a plan view showing the transistor with the insulating film omitted, Figure 2 is an enlarged plan view of part of the first factor, and Figure 3 is the third factor.
AA sectional view of the figure.

第4図は第2図のB−B断面図である。なお、各部の区
別ン明確にするために、第1図及び第2図の平面図、及
び追って述べる別の実施例におち・て。
FIG. 4 is a sectional view taken along line BB in FIG. In order to clearly distinguish between each part, we will refer to the plan views of FIGS. 1 and 2 and other embodiments to be described later.

エミッタ及びベース接続導体睡αηに斜線が付けられて
いる。
The emitter and base connecting conductors αη are shaded.

図において、αDはN型(第1の導電型)エミッタ領域
、σZはP型(第2の導電型ンベース領域、a&はNu
高抵抗コレクタ領域、 [41は琳抵抗コレクタ領域、
  (15a)(15b)はAI膜から成る第1及び第
2のエミッタ配線導体、 (16a)(36b丹まエミ
ッタ接続1に極、 (17a)はAI膜から成るベース
配線導体。
In the figure, αD is an N-type (first conductivity type) emitter region, σZ is a P-type (second conductivity type) base region, and a& is Nu
High resistance collector region, [41 is Rin resistance collector region,
(15a) and (15b) are first and second emitter wiring conductors made of an AI film; (16a) and (36b) are poles for emitter connection 1; (17a) are base wiring conductors made of an AI film.

u8はポリシリコン膜から成るエミッタ安定化抵抗、σ
lはNi膜から成るコレクタ1優、(20)はSin、
−8i。
u8 is an emitter stabilizing resistor made of polysilicon film, σ
l is a collector made of Ni film, (20) is Sin,
-8i.

R4の2層膜から成る絶縁膜、C+11(221Ωは絶
縁膜翰に設けた開孔である。
An insulating film consisting of a two-layer film of R4, C+11 (221Ω is an opening provided in the insulating film ridge).

エミッタ領waIIは島状に配列された多数の単位エミ
ッタ領域(11a) y!′含み、ベース領域α力はチ
ップ表面においてメツシュ状に配置されている。第1図
には単位エミッタ領域(tla)が12個のみ示されて
いるが、実際にはもつと多(例えば200個設けられて
いる。
The emitter area waII is a large number of unit emitter areas (11a) arranged like islands y! ′, the base region α force is arranged like a mesh on the chip surface. Although only 12 unit emitter regions (tla) are shown in FIG. 1, in reality there are many (for example, 200).

各単位エミッタ領域(11a)に対応して第1及び第2
のエミッタ配線導体(15a)(15b)が設けられ、
更にこれ等乞共通に接続する共通接続部(15C)が設
けられている。第1及び第2のエミッタ配線導体(15
a)(15b)は、絶縁膜端に設けられた第1及び第2
のエミッタ接続用開孔口のを結ぶ第1σ)直線り、に対
して平行であり、且つ等しい間隔ン有する。
The first and second portions correspond to each unit emitter region (11a).
emitter wiring conductors (15a) (15b) are provided,
Furthermore, a common connection part (15C) is provided to connect these parts in common. First and second emitter wiring conductors (15
a) (15b) is the first and second portion provided at the edge of the insulating film.
It is parallel to the first σ line connecting the emitter connection openings of , and has an equal spacing.

ベース配線導体(17a)は、、エミッタ配線導体(1
5aJ(lsb)に平行に延びろように設けられ、絶縁
膜■に設けられたベース接続用開孔c!31ヲ介してベ
ース領域睦に接続されている。なお、各ベース配線導体
(17a)は共通接続部分(17b)に接続されている
。また、開孔のは、単位エミッタ領域(11a)の角に
対応して設けられている。
The base wiring conductor (17a) is the emitter wiring conductor (1
5aJ (lsb) and extends parallel to the base connection hole c! provided in the insulating film ■! It is connected to the base area via 31. Note that each base wiring conductor (17a) is connected to a common connection portion (17b). Further, the openings are provided corresponding to the corners of the unit emitter region (11a).

エミッタ安定化抵抗膜aeは略十字状に形成され、第1
及び第2の開孔の[相]のエミッタ接続電極(16a)
(16b)に接続されていると共に、第1及び第2のエ
ミッタ配線導体(15a)(15b)に接続されている
The emitter stabilizing resistive film ae is formed in a substantially cross shape, and the first
and the emitter connection electrode (16a) of the [phase] of the second opening.
(16b), and is also connected to the first and second emitter wiring conductors (15a) and (15b).

第1及び第2の開孔1211I221は単位エミッタ領
域(11a)の−万の方向における二等分線に対応する
第1のM線り、上に設けられ、且つ他方の方向における
二等分線に対応する第2の@線り、かう等しい距離上に
設けられている。なR1第2の直線り、は第1の直aL
1に直交し、第1の開孔口と第2の開孔のとの間の中央
を通っている。エミッタ安定化抵抗膜賭は、第1及び第
2の直線Lx、Ltya’中心に対称に形成されて−・
る。このエミッタ安定化抵抗膜賭の第1の直線LIに沿
う領域の一端部(]sa)は第1のエミッタ接続を極(
16a)に接続され、他端部(18b)は第2のエミッ
タ接続11葎(16b)に接続され、第2の直線り、に
沿う領域の一端部(4sc)は第1の工ミッタ配線導体
(15a)に接続され、他端部(18d)は第2のエミ
ッタ配線導体(15b)、に接続されている。
The first and second openings 1211I221 are provided above the first M line corresponding to the bisector of the unit emitter region (11a) in the -10,000 direction, and are provided above the bisector of the unit emitter region (11a) in the other direction. A second @ line corresponding to the above is provided at an equal distance. R1 is the second straight line, is the first straight line aL
1 and passes through the center between the first aperture opening and the second aperture. The emitter stabilizing resistive film is formed symmetrically around the first and second straight lines Lx and Ltya'.
Ru. One end (]sa) of the region along the first straight line LI of this emitter stabilizing resistive film connects the first emitter connection to the pole (
16a), the other end (18b) is connected to the second emitter connection 11 (16b), and one end (4sc) of the area along the second straight line is connected to the first emitter wiring conductor. (15a), and the other end (18d) is connected to a second emitter wiring conductor (15b).

上述の如く構成されたトランジスタに第5図に示す如き
波形24)のベース電流乞流してスイッチング動作させ
、二次破壊させるコレクタ電流工s/B(平均化された
値フヲ求めた。この際、コレクタ・エミッタ間にダイオ
ードクランプの方法によって5oovのt圧’t−m、
it、、負荷トL’CL=208mHのコイルχ接続し
、第5図の正方向ベース電流I  ’に2.5Aに固定
し、この正号向ベース電流IBsT のパルス幅W′PK:変えることによってコレクタ電流
1oyal−変化させて破壊に至るコレクタ電流IS/
Bの値を測定した。なお、逆方向のベース電流■B、の
値を−1,OA、 −2゜OA、−3,OAの3段階に
変化させ、それぞれの■  馨求めた。
A base current of waveform 24 as shown in FIG. 5 is caused to flow through the transistor configured as described above to perform switching operation, and the collector current s/B (averaged value value) to cause secondary destruction was determined. At this time, t pressure 't-m of 5oov by diode clamp method between collector and emitter,
It,, connect the coil χ with load L'CL = 208 mH, fix the positive direction base current I' in Fig. 5 to 2.5A, and change the pulse width W'PK of this positive direction base current IBsT. Collector current IS/
The value of B was measured. The value of the reverse base current (B) was varied in three steps: -1, OA, -2° OA, and -3, OA, and the respective values were determined.

7B この結果、IB、=−1,OAの時のTs/Bは]2Δ
7B As a result, Ts/B when IB, = -1, OA is ]2Δ
.

I=−2,OAの時のIs/Bは】】A。Is/B when I=-2, OA is】】A.

IB、=−0,3Aの時のT6/BはIOAであった。T6/B when IB,=-0.3A was IOA.

比較のために、抵抗膜Ql’設けない他は第1の実施例
と同一にしてI   Ylffl+定したところ、都。
For comparison, IYlffl+ was determined in the same manner as in the first embodiment except that the resistive film Ql' was not provided.

S/B =−1,OAの時のIs/Bは2Aであり、 IB、 
=−2,OA及びI=−3,OAの時のI8/Bは2A
B! 未満であった。また、抵抗値は第1の実施例の抵抗膜(
181と同一であるが、パターンを第14図に示す抵抗
M(6)(7)とし、その他は第1の実施例と同一にし
てI−Y測定したところ、 S/B IB、=−:l、0Δの時の工S/Bは7A。
When S/B = -1, OA, Is/B is 2A, IB,
=-2, OA and I=-3, I8/B when OA is 2A
B! It was less than Moreover, the resistance value is the resistance film of the first example (
181, except that the pattern was changed to the resistors M(6) and (7) shown in FIG. 14, and the other parts were the same as in the first embodiment, and I-Y measurements were performed. S/B IB, =-: When l and 0Δ, the engineering S/B is 7A.

稲、=−2,OAの時のl87Bは2A。Rice, = -2, l87B when OA is 2A.

IB、=−3,OAの時のIs/Bは2Aであった。Is/B was 2A when IB,=-3,OA.

この測定結果から明らかな如<、 −、=−1,OAの
時にすでに二次破壊耐食の改善効果が現われ、IB!=
−2,OAの時九は大幅に改g!−される。この改善効
果は、第6−及び第7図を参照して既に説明した理由で
生じるものと思われる。
As is clear from these measurement results, the effect of improving secondary fracture corrosion resistance is already apparent when <, -, = -1, OA, and IB! =
-2, OA time nine has been significantly revised! - to be done. This improvement effect appears to occur for the reasons already explained with reference to FIGS. 6-7.

次に、第8図〜第11図に示す第2の実施例に係わるト
ランジスタを説明する。但し、この第2の実施例の図面
、及び後で述べる第12歯、第13−1及び第15図に
おいて第1囚〜第4−と共通する部分には同一の符号を
付してその説明を省略する。
Next, a transistor according to a second embodiment shown in FIGS. 8 to 11 will be explained. However, in the drawings of this second embodiment and the 12th tooth, 13-1, and 15, which will be described later, the same reference numerals are given to the parts common to the 1st to 4th cases, and the explanation thereof will be given. omitted.

この第2の実施例では、第1図〜第4因のポリシリコン
族のエミッタ安定化抵抗膜賭の代りに、Al膜から成る
エミッタ安定化抵抗膜關が設けられている。この抵抗M
Zは、エミッタ配線導体(15a)(15b) 、エミ
ッタ接続t % (Isa) (16b)と同じ材料(
Al)であるが、幅及び/又は厚み馨小さくシ。
In this second embodiment, an emitter stabilizing resistor film made of an Al film is provided in place of the emitter stabilizing resistor film of the polysilicon family shown in FIGS. 1 to 4. This resistance M
Z is the same material as the emitter wiring conductors (15a) (15b) and the emitter connection t% (Isa) (16b).
Al), but with a smaller width and/or thickness.

断面積χ小さくすることによって所望の抵抗値が得られ
るように形成されている。例えば、エミッタ配線導体(
15a)(15b)の幅が30μm、厚さが5μmであ
るの罠対して、抵抗膜關の幅は30μm。
It is formed so that a desired resistance value can be obtained by reducing the cross-sectional area χ. For example, emitter wiring conductor (
15a) (15b) has a width of 30 μm and a thickness of 5 μm, whereas the width of the resistive film is 30 μm.

厚さが1μmである。第8図〜第11図のトランジスタ
は、抵抗膜i2aの材料ビ変えた点ン除いて第1図〜第
4図のトランジスタと同一に構成されている。
The thickness is 1 μm. The transistors shown in FIGS. 8 to 11 have the same structure as the transistors shown in FIGS. 1 to 4, except that the material of the resistive film i2a is changed.

第2の実施例のトランジスタの二次破壊に至るコレクタ
電流■  を第1の実施例と同一方法で7B 測定したところ、 IB、=−1,OAの時の工、/Bは6A。
When the collector current (2) which leads to secondary breakdown of the transistor in the second embodiment was measured at 7B using the same method as in the first embodiment, when IB = -1 and OA, the current /B was 6A.

IB、=−2,OAの時のIS/Bは5A。IS/B is 5A when IB, = -2, OA.

1B、=−3,OAの時の■s/Bは5Aであった。■s/B when 1B, = -3, OA was 5A.

この結果から明らかな如<、IB、が大きい時。It is clear from this result that when <,IB, is large.

即ち深い逆バイアス時において二次破壊耐量の向上が紹
められた。第2の実施例においては、エミッタ安定化抵
抗MGの抵抗値が、第14図の従来の抵抗(6)(7)
の抵抗値、!:りも小さく、エミッタ安定化に対して不
利な値であるにも拘らず、深い逆バイアス時に二次破壊
耐量が向上するのは、抵抗膜■を十字状に形成したため
である。なお、このAIM乞近抗膜關とする場合には、
焼損によってエミッタがオープン状態になり、他のセル
の負担が増大し、破壊に至る。
In other words, an improvement in secondary breakdown resistance was introduced during deep reverse bias. In the second embodiment, the resistance value of the emitter stabilizing resistor MG is the same as that of the conventional resistors (6) and (7) in FIG.
The resistance value of,! The reason why the secondary breakdown resistance is improved during deep reverse biasing is that the resistive film (2) is formed in a cross shape, even though it is small and is a disadvantageous value for emitter stabilization. In addition, when using this AIM as a barrier,
Burnout causes the emitter to become open, increasing the burden on other cells and leading to their destruction.

本実施例の如く、抵抗膜口をエミッタ配線導体(15a
)(15b)等と同一材料とすれば、製造工程が節線化
され、コストダウンが可能になる。なお、第14因の構
造の抵抗(61(71ンこの第2の実施例と同様にAl
gで構成しようとすると、実用的長さの範囲で必要な抵
抗値を得ることが困難であり1例え必要な抵抗値が得ら
れても、二次破壊が起こり易(′。
As in this embodiment, the resistor film opening is connected to the emitter wiring conductor (15a
) (15b) etc., the manufacturing process can be simplified and costs can be reduced. Note that the resistance of the structure of the 14th factor (61 (71) is Al
If you try to configure it with g, it is difficult to obtain the necessary resistance value within a practical length range, and even if the necessary resistance value is obtained, secondary damage is likely to occur ('.

〔変形例〕[Modified example]

本発明は、上述の実施例に限定されるものでなく1例え
ば次の変形例が可能なものである。
The present invention is not limited to the embodiments described above, but the following modifications are possible, for example.

匹】 第12図及び第13図に示す如く、ベース領域a
カヲ島状に配置し、エミッタ領域C11lをメツシュ状
に配flしたメツシュエミッタ型トランジスタ(ベース
アイランド型トランジスタ〕にも本発明ン適用すること
が可能である。この場合には、単位エミッタ領域Uta
)に対応させて第1及び第2の開孔Gl+のを設け、こ
れと第1及び第2のエミッタ配線導体(15a)(15
b)との間釦第12図に示す如く第1の実施例と同一の
ポリシリコン膜の抵抗膜Cl8)ン設けるか、又は第1
3図釦示す如く第2の実施例と同一のAI膜の抵抗M■
ン設ける。これにより、第1及び第2の実施例と全く同
様な作用効果が得られる。
] As shown in Figures 12 and 13, the base area a
The present invention can also be applied to a mesh emitter type transistor (base island type transistor) in which the emitter region C11l is arranged in a mesh shape.In this case, the unit emitter region Uta
) are provided corresponding to the first and second openings Gl+, and these and the first and second emitter wiring conductors (15a) (15
As shown in FIG. 12, between the button b) and the first
As shown in Figure 3, the resistance M of the AI film is the same as in the second embodiment.
Provide a link. As a result, the same effects as in the first and second embodiments can be obtained.

B+  第15図に示す如く、メツシュエミッタ型トラ
ンジスタにおいて、エミッタ接続用開孔1211の乞規
則正しく繰返して配置し、開孔(2Il)のそれぞれの
間に十字状のポリシリコン膜から成る抵抗膜賭又はAI
膜から成る抵抗膜を設けてもよい・この場合には、開孔
f211@が隣接する単位エミッタ領域(11aJと兼
用される。
B+ As shown in FIG. 15, in a mesh emitter type transistor, emitter connection openings 1211 are regularly and repeatedly arranged, and a resistive film made of a cross-shaped polysilicon film is placed between each opening (2Il). Or AI
A resistive film made of a film may be provided. In this case, the opening f211@ serves also as the adjacent unit emitter region (11aJ).

(0抵抗膜(181+331をポリシリコン、AI以外
の抵抗材料又は金属材料で形成してもよい。要する忙。
(0 resistance film (181+331) may be formed of polysilicon, a resistance material other than AI, or a metal material.

抵抗膜賭卿は、抵抗が得られる膜であれば、どの様な材
料でもよい。
The resistive film may be made of any material as long as it provides resistance.

0 抵抗膜α8c(31のパターンン正確な十字状とせ
ず%又M部分に曲藁娶つけた形状としてもよい。
0 Resistive film α8c (pattern 31) The pattern may not be exactly cross-shaped, but may also have a curved shape at the M portion.

また、抵抗膜(181r24Jの第1の直線り、に沿う
部分の長さ?、第2の直線り、に沿う部分の幅に近づけ
るか。
Also, is the length of the portion along the first straight line of the resistive film (181r24J?) close to the width of the portion along the second straight line?

又は等しくするようにパターンン変形してもよい。Alternatively, pattern deformation may be performed to make them equal.

[F] 抵抗Jiua+c(31’v開孔(211Ci
’21の中にも設け、エミッタ領域σBに直接に接続す
不ようにしてもよい。
[F] Resistance Jiua+c (31'v opening (211Ci
'21 as well, so as not to be directly connected to the emitter region σB.

〔発明の効果〕〔Effect of the invention〕

上述から明らかな如く1本発明に従って、一対の開孔を
結ぶ第1の直線に沿って抵抗膜Z設けると共に、第1の
直線に直交する第2の直線に沿っても抵抗y!ン設け、
この第2の直線にむう抵抗膜の両端ンエミッタ配線樽体
に接続すれば、抵抗膜か焼損し難(なり、二次破壊耐量
が向上する。
As is clear from the above, according to the present invention, the resistance film Z is provided along the first straight line connecting the pair of openings, and the resistance y! is also provided along the second straight line orthogonal to the first straight line. Provided with
If both ends of the resistive film are connected to the emitter wiring barrel along this second straight line, the resistive film will be less likely to burn out, and the secondary breakdown resistance will be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例のトランジスタを示す平
面内。 第2図は第1図の一部拡大平面図、 第3図は第2脂のA −A lfi F!ft面図。 第4図は第2図のB−B線断面図。 第5囚は二次破壊コレクタ電流を測定するための電流波
形図、 第6図は従来のエミッタ安定化抵抗における電流の流れ
万ン示す平面図。 第7図は本発明のエミッタ安定化抵抗膜における電流の
流れ方を示す平面図、 第8図は本発明の第2の実施例のトランジスタを示す平
面図、 第9−は第8図の一部拡大平面図、 第10図は第9図のA−A線断面図。 第11図は第9図のB−B線断面図。 第12図及び第13図は変形例のトランジスタ乞示す平
面図、 第14崗は従来のトランジスタの一部χ示す平面図、 第15囚は変形例のトランジスタの一部?示す平面図で
ある。 111l・・・エミッタ領域、  (11a)・・・単
位エミッタ領域。 α力・・・ベース領域、α3・・・コレクタ領域、(1
5a)(15b)・・・エミッタ配線導体、賭・・・エ
ミッタ安定化抵抗膜。 (2昧・・・絶縁膜、c:n(221・・・開孔。
FIG. 1 is a plan view showing a transistor according to a first embodiment of the present invention. Fig. 2 is a partially enlarged plan view of Fig. 1, and Fig. 3 is the A-A lfi F! of the second fat. ft side view. FIG. 4 is a sectional view taken along the line B-B in FIG. 2. Figure 5 is a current waveform diagram for measuring the secondary breakdown collector current, and Figure 6 is a plan view showing the current flow in a conventional emitter stabilizing resistor. FIG. 7 is a plan view showing how current flows in the emitter stabilizing resistive film of the present invention, FIG. 8 is a plan view showing a transistor according to the second embodiment of the present invention, and FIG. FIG. 10 is a sectional view taken along the line A-A in FIG. 9; FIG. 11 is a sectional view taken along the line B-B in FIG. 9. Figures 12 and 13 are plan views showing a modified example of a transistor, Figure 14 is a plan view showing a portion of a conventional transistor, and Figure 15 is a plan view showing a portion of a modified transistor. FIG. 111l...Emitter region, (11a)...Unit emitter region. α force...base area, α3...collector area, (1
5a) (15b)...Emitter wiring conductor, bet...Emitter stabilizing resistive film. (2) Insulating film, c:n (221... Opening.

Claims (5)

【特許請求の範囲】[Claims] (1)第1の導電型のコレクタ領域と、 前記コレクタ領域に隣接している第2の導電型のベース
領域と、 前記ベース領域に前記コレクタ領域とは反対側において
隣接するように配置され、且つ複数の島状部分又は網状
部分又はストライプ状部分を有している第1の導電型の
エミッタ領域と、 前記エミッタ領域及び前記ベース領域の表面上に設けら
れている絶縁膜と、 前記エミッタ領域を構成する複数の単位エミッタ領域上
の前記絶縁膜にそれぞれ設けられたエミッタ接続用開孔
と、 前記複数の単位エミッタ領域を並列接続するためのエミ
ッタ配線導体と、 前記ベース領域に接続されたベース配線導体と、前記単
位エミッタ領域と前記エミッタ配線導体との間に設けら
れた抵抗膜と を有するマルチセル型トランジスタにおいて、前記単位
エミッタ領域(11a)に対応させて第1及び第2のエ
ミッタ接続用開孔(21)(22)設け、前記第1のエ
ミッタ接続用開孔(21)の中心と前記第2のエミッタ
接続用開孔(22)の中心とを結ぶ第1の直線に沿う領
域及び前記第1及び第2のエミッタ接続用開孔(21)
(22)間の略中央で前記第1の直線に直交する第2の
直線に沿う領域に抵抗膜(18)(33)を設け、前記
第1の直線に沿う領域の抵抗膜の両端部を前記第1及び
第2のエミッタ接続用開孔(21)(22)を通して直
接に又はエミッタ接続電極(16a)(16b)を介し
て前記単位エミッタ領域(11a)にそれぞれ接続し、
前記第2の直線に沿う領域の抵抗膜の両端部を前記エミ
ッタ配線導体(15a)(15b)にそれぞれ接続した
ことを特徴とするマルチセル型トランジスタ。
(1) a collector region of a first conductivity type; a base region of a second conductivity type adjacent to the collector region; arranged adjacent to the base region on a side opposite to the collector region; and a first conductivity type emitter region having a plurality of island-like portions, net-like portions, or stripe-like portions; an insulating film provided on surfaces of the emitter region and the base region; and the emitter region. Emitter connection holes provided in the insulating film on the plurality of unit emitter regions constituting the plurality of unit emitter regions, an emitter wiring conductor for connecting the plurality of unit emitter regions in parallel, and a base connected to the base region. In a multi-cell type transistor having a wiring conductor and a resistive film provided between the unit emitter region and the emitter wiring conductor, first and second emitter connection portions are provided corresponding to the unit emitter region (11a). an area along a first straight line connecting the center of the first emitter connection hole (21) and the center of the second emitter connection hole (22); The first and second emitter connection holes (21)
A resistive film (18) and (33) are provided in a region along a second straight line perpendicular to the first straight line at approximately the center between (22) and both ends of the resistive film in the region along the first straight line. connected to the unit emitter region (11a) directly through the first and second emitter connection openings (21) (22) or via emitter connection electrodes (16a) (16b),
A multi-cell transistor characterized in that both ends of the resistive film in the region along the second straight line are connected to the emitter wiring conductors (15a) (15b), respectively.
(2)前記抵抗膜は、前記エミッタ配線導体(15a)
(15b)と異なる材料から成るものである特許請求の
範囲第1項記載のマルチセル型トランジスタ。
(2) The resistive film is connected to the emitter wiring conductor (15a)
The multi-cell transistor according to claim 1, which is made of a material different from (15b).
(3)前記抵抗膜がポリシリコン膜である特許請求の範
囲第2項記載のマルチセル型トランジスタ。
(3) The multi-cell transistor according to claim 2, wherein the resistive film is a polysilicon film.
(4)前記抵抗膜が前記エミッタ配線導体(15a)(
15b)と同じ材料から成り、その断面積が前記エミッ
タ配線導体(15a)(15b)のそれよりも小さくさ
れたものである特許請求の範囲第1項記載のマルチセル
型トランジスタ。
(4) The resistive film is connected to the emitter wiring conductor (15a) (
2. The multi-cell transistor according to claim 1, which is made of the same material as the emitter wiring conductors (15b) and has a cross-sectional area smaller than that of the emitter wiring conductors (15a) and (15b).
(5)前記抵抗膜及び前記エミッタ配線導体が共にAl
膜である特許請求の範囲第4項記載のマルチセル型トラ
ンジスタ。
(5) Both the resistive film and the emitter wiring conductor are made of Al.
5. The multi-cell transistor according to claim 4, which is a film.
JP6038985A 1985-03-25 1985-03-25 Multi-cell type transistor Granted JPS61219171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6038985A JPS61219171A (en) 1985-03-25 1985-03-25 Multi-cell type transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6038985A JPS61219171A (en) 1985-03-25 1985-03-25 Multi-cell type transistor

Publications (2)

Publication Number Publication Date
JPS61219171A true JPS61219171A (en) 1986-09-29
JPH0329299B2 JPH0329299B2 (en) 1991-04-23

Family

ID=13140740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6038985A Granted JPS61219171A (en) 1985-03-25 1985-03-25 Multi-cell type transistor

Country Status (1)

Country Link
JP (1) JPS61219171A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63211673A (en) * 1987-02-26 1988-09-02 Shindengen Electric Mfg Co Ltd Power transistor
JP2002334888A (en) * 2001-05-08 2002-11-22 Sanken Electric Co Ltd Semiconductor device and manufacturing method therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516427A (en) * 1978-07-21 1980-02-05 Toshiba Corp Method of manufacturing semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516427A (en) * 1978-07-21 1980-02-05 Toshiba Corp Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63211673A (en) * 1987-02-26 1988-09-02 Shindengen Electric Mfg Co Ltd Power transistor
JP2002334888A (en) * 2001-05-08 2002-11-22 Sanken Electric Co Ltd Semiconductor device and manufacturing method therefor

Also Published As

Publication number Publication date
JPH0329299B2 (en) 1991-04-23

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