JPH0536279Y2 - - Google Patents

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Publication number
JPH0536279Y2
JPH0536279Y2 JP1986073391U JP7339186U JPH0536279Y2 JP H0536279 Y2 JPH0536279 Y2 JP H0536279Y2 JP 1986073391 U JP1986073391 U JP 1986073391U JP 7339186 U JP7339186 U JP 7339186U JP H0536279 Y2 JPH0536279 Y2 JP H0536279Y2
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JP
Japan
Prior art keywords
region
type emitter
regions
semiconductor substrate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP1986073391U
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Japanese (ja)
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JPS62184759U (en
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Description

【考案の詳細な説明】 〔産業上の利用分野〕 この考案は、ゲートへの信号入力により、オフ
状態からオン状態、オン状態からオフ状態へ連続
的に制御し得るゲートターンオフサイリスタに関
するものである。
[Detailed description of the invention] [Industrial application field] This invention relates to a gate turn-off thyristor that can be controlled continuously from an off state to an on state and from an on state to an off state by inputting a signal to the gate. .

〔従来の技術〕[Conventional technology]

従来例によるこの種のゲートターンオフサイリ
スタとして、特開昭57−115866号公報に開示され
た逆導通型ゲートターンオフサイリスタの構成を
第3図a,bに示す。同図aはゲートターンオフ
サイリスタのカソード電極とゲート電極のパター
ン図、同図bは同上A−A線部における一つのn
形エミツタ領域部分の断面図である。
As a conventional example of this type of gate turn-off thyristor, the structure of a reverse conduction type gate turn-off thyristor disclosed in Japanese Patent Application Laid-Open No. 115866/1982 is shown in FIGS. 3a and 3b. Figure a is a pattern diagram of the cathode electrode and gate electrode of the gate turn-off thyristor, Figure b is one of the patterns of the gate turn-off thyristor at
FIG. 3 is a cross-sectional view of a portion of a shaped emitter region.

すなわち、これらの第3図a,bに示す従来例
構造おいて、符号100は所定の直径を有する半
導体基体を表わしている。また1a,1bは多数
個の短冊類似形状に分離され、かつ放射状方向に
多列状に配置された、n形エミツタ領域(nE)、
2はnE領域1a,1bに隣接されたp形ベース領
域(pB)、3はpB領域2に隣接されたn形ベース
領域(nB)、4はn領域3に隣接された、p形エ
ミツタ領域(pE)であり、さらに5a,5bと
6、および7はこれらのnE領域1a,1bとpB
域2、およびpE領域4にオーミツク接触して形成
されたそれぞれカソード電極、ゲート電極、およ
びアノード電極である。
That is, in the conventional structure shown in FIGS. 3a and 3b, the reference numeral 100 represents a semiconductor substrate having a predetermined diameter. 1a and 1b are n-type emitter regions (n E ) separated into a large number of strip-like shapes and arranged in multiple rows in the radial direction;
2 is a p-type base region ( pB ) adjacent to nE regions 1a and 1b, 3 is an n-type base region ( nB ) adjacent to pB region 2, 4 is adjacent to n-region 3, 5a, 5b, 6, and 7 are p-type emitter regions ( pE ), and cathodes 5a, 5b, 6, and 7 are formed in ohmic contact with these nE regions 1a, 1b, pB region 2, and pE region 4, respectively. electrode, gate electrode, and anode electrode.

なお、図中、符号θは中心部側での各nE領域1
aの相互間のなす角度である。
In addition, in the figure, the symbol θ indicates each n E area 1 on the center side.
This is the angle between a.

しかして、この従来例構成によるゲートターン
オフサイリスタの場合には、pE領域4からnE領域
1a,1bへ流れている電流をオフ状態にターン
オフさせるためには、カソード電極5に対して、
ゲート電極6に負の電圧を加え、pB領域2中のキ
ヤリアをゲート電極6から引き出すことによつて
なされる。このオフ状態への移行現象をより詳細
に述べると、pE領域4からnE領域1a,1bに流
れている正孔は、pB領域2を通過する際に、ゲー
ト電極6に近いものから順次に引き出され、nE
域1a,1bの中心部に絞り込まれてオフ状態に
至もので、従つてこのターンオフ特性には、nE
域1a,1bの中心部からゲート電極6までのpB
領域2の横方向抵抗成分が大きく影響することに
なる。
In the case of the gate turn-off thyristor having this conventional structure, in order to turn off the current flowing from the pE region 4 to the nE regions 1a and 1b to the off state, the cathode electrode 5 must be
This is done by applying a negative voltage to the gate electrode 6 and drawing out the carriers in the p B region 2 from the gate electrode 6. To explain this transition phenomenon to the OFF state in more detail, the holes flowing from the pE region 4 to the nE regions 1a and 1b, when passing through the pB region 2, The turn -off characteristic is caused by the p B
The lateral resistance component of region 2 has a large influence.

〔考案が解決しようとする問題点〕[Problem that the invention attempts to solve]

従来例によるゲートターンオフサイリスタは前
記構成からなるために、ターンオフ特性を損なわ
ずに、制御可能な電流を大きくするのには、短冊
状に分離されている多数構成のnE領域1a,1b
を可及的に詰めて配置するなど、nE領域1a,1
bの全面積を増加させる必要がある。そこで、こ
のための一つの手段として、nE領域1a,1bの
幅を扇形に拡げる手段(例えば特開昭60−241264
号に開示されている)が考えられるが、このよう
な手段では、拡げた部分相応に横方向抵抗成分が
大きくなり、却つてターンオフ特性を悪くさせる
惧れがあり、また多列に亘る放射状方向のnE領域
1a,1bの中心に近い方のnE領域1aを短く、
かつその角度θを小さく配置しても、元来、この
中心に近い方のnE領域1aの個数が少なくて、こ
れらのnE領域1a,1bの全面積を大幅に拡げる
ことにはならないなどの問題点があつた。
Since the conventional gate turn-off thyristor has the above-mentioned configuration, in order to increase the controllable current without impairing the turn-off characteristics, a large number of n E regions 1a and 1b separated into strips are required.
n E area 1a, 1
It is necessary to increase the total area of b. Therefore, one means for this purpose is to expand the width of the nE regions 1a and 1b into a fan shape (for example, in Japanese Patent Application Laid-Open No. 60-241264
However, with such means, the lateral resistance component increases in proportion to the expanded portion, which may actually worsen the turn-off characteristics, and the radial direction Shorten the n E area 1a, which is closer to the center of the n E areas 1a and 1b,
And even if the angle θ is arranged small, the number of n E regions 1a closer to the center is originally small, and the total area of these n E regions 1a and 1b will not be significantly expanded. There was a problem.

この考案は、従来のこのような問題点を改善す
るためになされたものであつて、その目的とする
ところは、ターンオフ特性を損なわずに、より大
電流を開閉制御し得るようにしたゲートターンオ
フサイリスタを提供することである。
This invention was made in order to improve these conventional problems, and its purpose is to create a gate turn-off system that can control opening and closing of a larger current without impairing the turn-off characteristics. It is to provide a thyristor.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的を達成するために、この考案に係るゲ
ートターンオフサイリスタは、各n形エミツタ領
域の短冊類似形状をして、短冊類似形状の対向す
る長辺の放射状方向先端側に並行部を設け、この
並行部から半導体基体の中心部に向けて、対向す
る長辺間の幅が直線状に狭まるように形成させ
て、隣接するn形エミツタ領域相互の間隔を詰め
ることにより、n形エミツタ領域の個数を増加さ
せ、結果的に半導体基体上に占めるn形エミツタ
領域の全面積の割合を増加させるようにしたもの
である。
In order to achieve the above object, the gate turn-off thyristor according to this invention has each n-type emitter region shaped like a strip, and a parallel portion is provided on the tip side in the radial direction of the opposite long side of the strip-like shape. The number of n-type emitter regions can be reduced by narrowing the distance between adjacent n-type emitter regions by forming them so that the width between opposing long sides narrows linearly from the parallel portion toward the center of the semiconductor substrate. This increases the ratio of the total area of the n-type emitter region on the semiconductor substrate.

〔作用〕[Effect]

従つて、この考案においては、各n形エミツタ
領域での短冊類似形状の放射状方向先端側で対向
する長辺間の幅が拡がらないので、装置自体のタ
ーンオフ特性を損なう惧れがなく、併せて全面積
の増加相当分だけ、大きな電流の開閉制御をなし
得るのである。
Therefore, in this invention, since the width between the opposing long sides on the radially distal end side of the strip-like shape in each n-type emitter region does not increase, there is no risk of damaging the turn-off characteristics of the device itself; Therefore, it is possible to control the opening and closing of a large current by the amount corresponding to the increase in the total area.

〔実施例〕〔Example〕

以下、この考案に係るゲートターンオフサイリ
スタの一実施例につき、第1図および第2図を参
照して詳細に説明する。
Hereinafter, one embodiment of the gate turn-off thyristor according to this invention will be described in detail with reference to FIGS. 1 and 2.

第1図はこの実施例を適用したゲートターンオ
フサイリスタの、前記第3図aに対応したパター
ン平面図、第2図は同上相互に隣接するn形エミ
ツタ領域パターン要部の拡大図であり、これらの
各図中、同一符号は同一または相当部分を示して
いる。
FIG. 1 is a pattern plan view of a gate turn-off thyristor to which this embodiment is applied, corresponding to FIG. In each figure, the same reference numerals indicate the same or corresponding parts.

この実施例では、半導体基体101上に、前記
多列に亘り配設される各nE領域1a,1bにおい
て、その短冊類似形状を、短冊類似形状の対向す
る長辺の放射状方向先端側に並行部を設け、この
並行部から半導体基体101の中心部に向けて、
対向する長辺間の幅が直線状に狭まるように形成
させると共に、隣接するnE領域1aおよび1bそ
れぞれの相互の間隔を可及的に接近させることに
よつて、全体としてのnE領域1a,1bの個数を
増加させるようにし、その結果として、半導体基
体101上に占めるnE領域1a,1bの全面積の
割合を効果的に増加させたものである。
In this embodiment, in each of the n E regions 1a and 1b arranged in multiple rows on the semiconductor substrate 101, the strip-like shape is parallel to the radial direction tip side of the opposing long side of the strip-like shape. A section is provided, and from this parallel section toward the center of the semiconductor substrate 101,
By forming the width between the opposing long sides to narrow linearly and by making the mutual spacing between the adjacent n E regions 1a and 1b as close as possible, the n E region 1a as a whole can be improved. , 1b is increased, and as a result, the proportion of the total area occupied by n E regions 1a, 1b on semiconductor substrate 101 is effectively increased.

すなわち、この実施例の場合には、半導体基体
101の中心部0から、これに近い方のnE領域1
aまでの距離をr1、次式のnE領域1bまでの距離
をr2、これらの各nE領域1a,1bの長さをl、
同幅をwとし、かつ中心部0に対するnE領域1a
の角度をθ1、nE領域1bの角度をθ2としたとき、
これらの各nE領域1a,1bの短冊類似形状の両
長辺側の途上、こゝでは中間点l/2から、同半導
体基体101の中心部側に向けて、その幅、つま
りパターン幅が次第に狭まるように形成させ、こ
の挟まつた部分の間隔をdとしたものである。
That is, in the case of this embodiment, from the center 0 of the semiconductor substrate 101 to the n E region 1 closer to this
The distance to a is r 1 , the distance to the n E area 1b in the following equation is r 2 , the length of each of these n E areas 1a and 1b is l,
Let w be the same width, and n E area 1a with respect to the center 0
When the angle of is θ 1 and the angle of n E region 1b is θ 2 ,
In the middle of both long sides of the strip-like shape of each of these nE regions 1a and 1b, the width, that is, the pattern width, increases from the midpoint l/2 toward the center of the semiconductor substrate 101. It is formed so that it gradually narrows, and the interval between the sandwiched portions is defined as d.

仍つて、この実施例構造においては、nE領域1
aについてみるとき、r1=5mm,l=3mm,d=
0.1mm,w=0.36mmとした場合、前記第3図a従
来例でのnE領域1aの配置個数が70本であつたの
に、これを84本まで増加でき、かつ同面積を13.5
%相当分だけ増加し得られ、また、nE領域1bに
ついては、同様にr2=8.2mmとした場合、従来例
でのnE領域1bの配置個数が228本であつたのに、
これを256本まで増加でき、かつ同面積を8.2%相
当分だけ増加し得るのである。
In addition, in this embodiment structure, n E region 1
When considering a, r 1 = 5 mm, l = 3 mm, d =
0.1 mm, w = 0.36 mm, the number of arranged n E regions 1a in the conventional example in Fig. 3a was 70, but this can be increased to 84, and the same area can be reduced to 13.5.
Similarly, when r 2 = 8.2 mm for the n E region 1b, the number of wires arranged in the n E region 1b in the conventional example was 228.
This can be increased to 256 lines, and the same area can be increased by 8.2%.

なお、前記実施例では、各nE領域1a,1bで
の短冊類似形状の両長辺側の中間点l/2から、半
導体基体101の中心部側に向けて、そのパター
ン幅が次第に狭まるように形成させているが、必
ずしもパターン幅を狭め始める起点を中間点l/2
とする必要はなく、拡幅に伴なう各nE領域1a,
1bの横方向抵抗成分の増加を避けるべく、これ
に見合つて適宜に設定すれば良い。
In the above embodiment, the pattern width is gradually narrowed from the midpoint l/2 of both long sides of the strip-like shape in each nE region 1a, 1b toward the center of the semiconductor substrate 101. However, the starting point at which the pattern width begins to narrow is not necessarily set at the midpoint l/2.
There is no need to do this, and each n E area 1a,
In order to avoid an increase in the lateral resistance component of 1b, it may be set appropriately in accordance with this.

〔考案の効果〕[Effect of idea]

以上詳述したように、この考案によれば、所定
の直径を有する半導体基体上にあつて、放射状方
向に多列に亘つて配置される各n形エミツタ領域
の短冊類似形状を、短冊類似形状の対向する長辺
の放射状方向先端側に並行部を設け、この並行部
から半導体基体の中心部に向けて、対向する長辺
間の幅が直線上に狭まるように形成させて、隣接
するn形エミツタ領域相互の間隔を詰め得るよう
にしたので、同一直径の半導体基体上に配置され
るn形エミツタ領域の個数、ひいては半導体基体
上に占めるn形エミツタ領域の全面積の割合を増
加させることができると共に、徒らに、n形エミ
ツタ領域の幅が拡つて、横方向抵抗成分を大きく
するような惧れがなく、このためにターンオフの
際に短冊類似形状をしたn形エミツタ領域の、対
向する長辺の並行部の全長にわたつて、並行部の
幅中央で電流が線状に絞られて切られるから、点
状に絞られる電流集中が防止され電極の損傷が発
生せず開閉制御可能な電流を大きくでき、かつタ
ーンオフ特性などの電気的特性を充分に向上し得
るのであり、しかも構造的にも比較的簡単で、容
易に実施できるなどの優れた特長を有するもので
ある。
As detailed above, according to this invention, each n-type emitter region arranged in multiple rows in the radial direction on a semiconductor substrate having a predetermined diameter has a rectangular shape similar to a rectangular shape. A parallel portion is provided on the radial direction tip side of the opposing long sides, and the width between the opposing long sides narrows in a straight line from this parallel portion toward the center of the semiconductor substrate. Since the spacing between the n-type emitter regions can be reduced, the number of n-type emitter regions disposed on a semiconductor substrate having the same diameter and, as a result, the proportion of the total area occupied by the n-type emitter regions on the semiconductor substrate can be increased. At the same time, there is no fear that the width of the n-type emitter region will expand unnecessarily and increase the lateral resistance component, and for this reason, when turning off, the n-type emitter region, which has a shape similar to a strip, The current is condensed and cut in a line at the center of the width of the parallel part over the entire length of the parallel part on the opposing long sides, preventing the current from concentrating in a dotted shape, preventing electrode damage and opening/closing control. It has excellent features such as being able to increase the available current, sufficiently improving electrical characteristics such as turn-off characteristics, and being relatively simple in structure and easy to implement.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を適用した逆導通
型ゲートターンオフサイリスタの構成を示すパタ
ーン平面図、第2図は同上相互に隣接するn形エ
ミツタ領域ターン要部の拡大図であり、また第3
図a,bは従来例による逆導通型ゲートターンオ
フサイリスタの構成を示すパターン平面図、およ
び同上A−A線部の縦断面図である。 101……半導体基体、1a,1b……n形エ
ミツタ領域(nE領域)、2……p形ベース領域
(pB領域)、3……n形ベース領域(nB領域)、4
……p形エミツタ領域(pE領域)、5a,5b…
…カソード電極、6……ゲート電極、7……アノ
ード電極。
FIG. 1 is a pattern plan view showing the configuration of a reverse conduction type gate turn-off thyristor to which an embodiment of the present invention is applied, and FIG. Third
Figures a and b are a pattern plan view showing the configuration of a conventional reverse conduction type gate turn-off thyristor, and a longitudinal cross-sectional view taken along line A--A of the same. 101... Semiconductor substrate, 1a, 1b... N-type emitter region (n E region), 2... P-type base region (p B region), 3... N-type base region (n B region), 4
...p-type emitter region (p E region), 5a, 5b...
... cathode electrode, 6 ... gate electrode, 7 ... anode electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体基体に、n形エミツタ領域、p形ベース
領域、n形べース領域、およびp形エミツタ領域
を順次に隣接形成させた4層構造にされ、前記n
形エミツタ領域を放射状方向に長辺が配設された
短冊類似形状にして、放射状に多列に亘り配設さ
せると共に、これらの各n形エミツタ領域上にカ
ソード電極、各カソード電極とは分離されて各n
形エミツタ領域を囲む前記p形ベース領域上にゲ
ート電極、および前記p形エミツタ領域上にアノ
ード電極をそれぞれに形成させたゲートターンオ
フサイリスタにおいて、前記各n形エミツタ領域
の短冊類似形状を、その対向する前記長辺の放射
状方向先端側に並行部を設け、この並行部から半
導体基体の中心部に向けて、対向する前記長辺間
の幅が直線状に狭まるように形成したことを特徴
とするゲートターンオフサイリスタ。
The semiconductor substrate has a four-layer structure in which an n-type emitter region, a p-type base region, an n-type base region, and a p-type emitter region are successively formed adjacent to each other;
The n-type emitter regions are shaped like strips with long sides arranged in a radial direction, and are arranged radially in multiple rows, and a cathode electrode is provided on each of these n-type emitter regions, separated from each cathode electrode. each n
In a gate turn-off thyristor in which a gate electrode is formed on the p-type base region surrounding a p-type emitter region, and an anode electrode is formed on the p-type emitter region, a rectangular-like shape of each n-type emitter region is formed on its opposite side. A parallel portion is provided on the radial direction tip side of the long side, and the width between the opposing long sides narrows linearly from the parallel portion toward the center of the semiconductor substrate. Gate turn-off thyristor.
JP1986073391U 1986-05-14 1986-05-14 Expired - Lifetime JPH0536279Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986073391U JPH0536279Y2 (en) 1986-05-14 1986-05-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986073391U JPH0536279Y2 (en) 1986-05-14 1986-05-14

Publications (2)

Publication Number Publication Date
JPS62184759U JPS62184759U (en) 1987-11-24
JPH0536279Y2 true JPH0536279Y2 (en) 1993-09-14

Family

ID=30917682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986073391U Expired - Lifetime JPH0536279Y2 (en) 1986-05-14 1986-05-14

Country Status (1)

Country Link
JP (1) JPH0536279Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2764830B2 (en) * 1989-09-14 1998-06-11 株式会社日立製作所 Gate turn-off thyristor
JP3580794B2 (en) 1999-06-29 2004-10-27 三菱電機株式会社 Power switching semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413274A (en) * 1977-07-01 1979-01-31 Internatl Rectifier Corp Japan Ltd Controlled rectifying element of semiconductor
JPS60241264A (en) * 1984-05-16 1985-11-30 Toshiba Corp Gate turn off thyristor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413274A (en) * 1977-07-01 1979-01-31 Internatl Rectifier Corp Japan Ltd Controlled rectifying element of semiconductor
JPS60241264A (en) * 1984-05-16 1985-11-30 Toshiba Corp Gate turn off thyristor

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JPS62184759U (en) 1987-11-24

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