JPS55153343A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS55153343A
JPS55153343A JP6123079A JP6123079A JPS55153343A JP S55153343 A JPS55153343 A JP S55153343A JP 6123079 A JP6123079 A JP 6123079A JP 6123079 A JP6123079 A JP 6123079A JP S55153343 A JPS55153343 A JP S55153343A
Authority
JP
Japan
Prior art keywords
layer
alumina
polycristalline
tendency
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6123079A
Other languages
Japanese (ja)
Inventor
Nobuo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6123079A priority Critical patent/JPS55153343A/en
Publication of JPS55153343A publication Critical patent/JPS55153343A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To make high integrated circuit available by a method wherein a dielectric isolation layer is formed by an oxide of a metal which have tendency of forming films and lessening of the film thickness. CONSTITUTION:An Al layer 9 which has tendency of forming films is fabricated on a sapphire substrate 1, and resist mask 10 is applied, and after the Al 9 is etched by phosphoric acid, an alumina wall 13 is formed by anodizing. The resist mask 10 is removed, and the Al 9 is removed by phosphoric acid, and on forming of an epitaxial layer 2 between alumina walls 13, a polycristalline Si layer 11 is generated on the alumina wall 13. Next thereto the polycristalline Si layer 11 is removed by grinding or by means of fluoric acid or its induced materials, and the surface of the alumina wall 13 is exposed. After this process an expected element is formed in a singl crystal layer 2. By this constitution in spite of thinness of the film of the dielectric isolation layer 13, an SOS device with high dielectric strength and high integration can be obtained.
JP6123079A 1979-05-18 1979-05-18 Semiconductor device and its manufacture Pending JPS55153343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6123079A JPS55153343A (en) 1979-05-18 1979-05-18 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6123079A JPS55153343A (en) 1979-05-18 1979-05-18 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS55153343A true JPS55153343A (en) 1980-11-29

Family

ID=13165201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6123079A Pending JPS55153343A (en) 1979-05-18 1979-05-18 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS55153343A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169964A (en) * 1982-03-30 1983-10-06 Fujitsu Ltd Semiconductor device
US4460413A (en) * 1980-12-26 1984-07-17 Nippon Telegraph & Telephone Public Corp. Method of patterning device regions by oxidizing patterned aluminum layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140767A (en) * 1974-10-03 1976-04-05 Fujitsu Ltd Handotaisochi no seizohoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140767A (en) * 1974-10-03 1976-04-05 Fujitsu Ltd Handotaisochi no seizohoho

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4460413A (en) * 1980-12-26 1984-07-17 Nippon Telegraph & Telephone Public Corp. Method of patterning device regions by oxidizing patterned aluminum layer
JPS58169964A (en) * 1982-03-30 1983-10-06 Fujitsu Ltd Semiconductor device
JPH0332232B2 (en) * 1982-03-30 1991-05-10 Fujitsu Ltd

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