JPS54144888A - Manufacture for gate control semiconductor element - Google Patents

Manufacture for gate control semiconductor element

Info

Publication number
JPS54144888A
JPS54144888A JP5358278A JP5358278A JPS54144888A JP S54144888 A JPS54144888 A JP S54144888A JP 5358278 A JP5358278 A JP 5358278A JP 5358278 A JP5358278 A JP 5358278A JP S54144888 A JPS54144888 A JP S54144888A
Authority
JP
Japan
Prior art keywords
diffusion
implanted region
type
entire surface
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5358278A
Other languages
Japanese (ja)
Inventor
Yasuo Kataoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP5358278A priority Critical patent/JPS54144888A/en
Publication of JPS54144888A publication Critical patent/JPS54144888A/en
Pending legal-status Critical Current

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  • Thyristors (AREA)

Abstract

PURPOSE: To simplify the process, by first forming the implanted region on the entire surface with diffusion, etching it into the specified pattern, and growing the epitaxial layer on the entire surface, in forming the implanted region on the semiconductor substrate on which PN junction is provided.
CONSTITUTION: The P type layers 20a and 20b are formed by diffusion at the both sides of the N type Si substrate 1, and all the surface is covered with the SiO2 folms 3a and 3b respectively. Next, one film 3a is selectively photo-etched to section it into a plurality of films 3a, and implantation is made by using mixture of nitric acid, acetic acid and hydrofluoric acid less in the mixture ratio of hydrofluoric acid, mesa etching is made form the implanted region consisting of the layer 20a under the film 3a. After that, the P- type layer 50 is epitaxially grown on the entire surface, the surface is made smoothed with polishing, and the N type emitter diffusion and the Au diffusion for life time extension are made normally. Thus, the formation of the implanted region can be very simpler.
COPYRIGHT: (C)1979,JPO&Japio
JP5358278A 1978-05-04 1978-05-04 Manufacture for gate control semiconductor element Pending JPS54144888A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5358278A JPS54144888A (en) 1978-05-04 1978-05-04 Manufacture for gate control semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5358278A JPS54144888A (en) 1978-05-04 1978-05-04 Manufacture for gate control semiconductor element

Publications (1)

Publication Number Publication Date
JPS54144888A true JPS54144888A (en) 1979-11-12

Family

ID=12946828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5358278A Pending JPS54144888A (en) 1978-05-04 1978-05-04 Manufacture for gate control semiconductor element

Country Status (1)

Country Link
JP (1) JPS54144888A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224360A (en) * 1987-03-13 1988-09-19 Meidensha Electric Mfg Co Ltd Manufacture of buried gate structure gate turn-off thyristor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224360A (en) * 1987-03-13 1988-09-19 Meidensha Electric Mfg Co Ltd Manufacture of buried gate structure gate turn-off thyristor

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