JPS54138368A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS54138368A
JPS54138368A JP4626478A JP4626478A JPS54138368A JP S54138368 A JPS54138368 A JP S54138368A JP 4626478 A JP4626478 A JP 4626478A JP 4626478 A JP4626478 A JP 4626478A JP S54138368 A JPS54138368 A JP S54138368A
Authority
JP
Japan
Prior art keywords
region
diffusion
layer
mask
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4626478A
Other languages
Japanese (ja)
Inventor
Isamu Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4626478A priority Critical patent/JPS54138368A/en
Publication of JPS54138368A publication Critical patent/JPS54138368A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE: To make small the semiconductor device in size, to obtain high performance and to increase the manufacturing yield, by determining the relation of position on the flat plane between the diffusion regions with the first mask through the use of the impurity diffusion mask of two layer construction and performing diffusion with the second mask.
CONSTITUTION: On the P type Si substrate 1 provided with the implanting layer 2, the N type layer 2 is epitaxially grown, and it is covered with the two layer construction diffusion mask with the SiO2 film 4 and the Si3N4 film 5. Further, on it, the resist mask 6 providing each region is provided, and the film 4 of each region is exposed by etching. After that, the mask 6 is renewed by etching and the specified region of the layer 3 is exposed, and the P type isolation region 7 is formed by diffusion in the layer 3. Further, the SiO2 film produced is patterned and the P type base region 8 and the resistor region 9 are formed by diffusion in the layer 3, and the N type collector contact region 10 is formed by diffusion with patterning again to provide the N type emitter region 11 in the region 8.
COPYRIGHT: (C)1979,JPO&Japio
JP4626478A 1978-04-19 1978-04-19 Manufacture for semiconductor device Pending JPS54138368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4626478A JPS54138368A (en) 1978-04-19 1978-04-19 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4626478A JPS54138368A (en) 1978-04-19 1978-04-19 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS54138368A true JPS54138368A (en) 1979-10-26

Family

ID=12742342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4626478A Pending JPS54138368A (en) 1978-04-19 1978-04-19 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54138368A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759319A (en) * 1980-09-29 1982-04-09 Hitachi Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759319A (en) * 1980-09-29 1982-04-09 Hitachi Ltd Manufacture of semiconductor device

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