JPS54128689A - Method of forming contact area between polycrystal sllicon layers - Google Patents

Method of forming contact area between polycrystal sllicon layers

Info

Publication number
JPS54128689A
JPS54128689A JP1989579A JP1989579A JPS54128689A JP S54128689 A JPS54128689 A JP S54128689A JP 1989579 A JP1989579 A JP 1989579A JP 1989579 A JP1989579 A JP 1989579A JP S54128689 A JPS54128689 A JP S54128689A
Authority
JP
Japan
Prior art keywords
sllicon
polycrystal
layers
contact area
forming contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989579A
Other languages
English (en)
Inventor
Samueru Riyuu Shiiauumingu
Deii Pashiyurei Richiyaado
Eichi Ooen Saado Uiriamu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JPS54128689A publication Critical patent/JPS54128689A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
JP1989579A 1978-03-27 1979-02-23 Method of forming contact area between polycrystal sllicon layers Pending JPS54128689A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/890,139 US4178674A (en) 1978-03-27 1978-03-27 Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor

Publications (1)

Publication Number Publication Date
JPS54128689A true JPS54128689A (en) 1979-10-05

Family

ID=25396309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989579A Pending JPS54128689A (en) 1978-03-27 1979-02-23 Method of forming contact area between polycrystal sllicon layers

Country Status (6)

Country Link
US (1) US4178674A (ja)
JP (1) JPS54128689A (ja)
DE (1) DE2911132A1 (ja)
GB (1) GB2017402B (ja)
HK (1) HK14185A (ja)
SG (1) SG78884G (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115858A (en) * 1981-01-08 1982-07-19 Nec Corp Semiconductor device
JPS58130554A (ja) * 1982-01-28 1983-08-04 Toshiba Corp 半導体装置の製造方法
JPS58501485A (ja) * 1981-09-14 1983-09-01 エヌ・シー・アール・インターナショナル・インコーポレイテッド 半導体基板の領域間に電気接触部を形成する方法

Families Citing this family (47)

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US4416049A (en) * 1970-05-30 1983-11-22 Texas Instruments Incorporated Semiconductor integrated circuit with vertical implanted polycrystalline silicon resistor
US4268951A (en) * 1978-11-13 1981-05-26 Rockwell International Corporation Submicron semiconductor devices
US4333225A (en) * 1978-12-18 1982-06-08 Xerox Corporation Method of making a circular high voltage field effect transistor
US4475964A (en) * 1979-02-20 1984-10-09 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US4285117A (en) * 1979-09-06 1981-08-25 Teletype Corporation Method of manufacturing a device in a silicon wafer
US4267632A (en) * 1979-10-19 1981-05-19 Intel Corporation Process for fabricating a high density electrically programmable memory array
JPS5662353A (en) * 1979-10-29 1981-05-28 Toshiba Corp Semiconductor device and its manufacturing method
JPS5696850A (en) * 1979-12-30 1981-08-05 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
US4282648A (en) * 1980-03-24 1981-08-11 Intel Corporation CMOS process
JPS6046545B2 (ja) * 1980-05-16 1985-10-16 日本電気株式会社 相補型ｍｏｓ記憶回路装置
US4691219A (en) * 1980-07-08 1987-09-01 International Business Machines Corporation Self-aligned polysilicon base contact structure
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
JPS5936432B2 (ja) * 1980-08-25 1984-09-04 株式会社東芝 半導体装置の製造方法
US4419808A (en) * 1980-12-15 1983-12-13 Rockwell International Corporation Method of producing redundant ROM cells
DE3204054A1 (de) * 1981-02-23 1982-09-09 Intel Corp., Santa Clara, Calif. Widerstand in integrierter schaltungstechnik und verfahren zu dessen herstellung
US4353159A (en) * 1981-05-11 1982-10-12 Rca Corporation Method of forming self-aligned contact in semiconductor devices
US4608668A (en) * 1981-09-03 1986-08-26 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device
JPS5893347A (ja) * 1981-11-30 1983-06-03 Toshiba Corp Ｍｏｓ型半導体装置及びその製造方法
JPS5974677A (ja) * 1982-10-22 1984-04-27 Ricoh Co Ltd 半導体装置及びその製造方法
US4505026A (en) * 1983-07-14 1985-03-19 Intel Corporation CMOS Process for fabricating integrated circuits, particularly dynamic memory cells
IT1196997B (it) * 1986-07-25 1988-11-25 Sgs Microelettronica Spa Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati
JPS63136668A (ja) * 1986-11-28 1988-06-08 Fuji Electric Co Ltd 半導体装置の製造方法
US5164338A (en) * 1988-04-28 1992-11-17 U.S. Philips Corporation Method of manufacturing a polycrystalline semiconductor resistance layer of silicon on a silicon body and silicon pressure sensor having such a resistance layer
EP0369336A3 (en) * 1988-11-14 1990-08-22 National Semiconductor Corporation Process for fabricating bipolar and cmos transistors on a common substrate
US5126279A (en) * 1988-12-19 1992-06-30 Micron Technology, Inc. Single polysilicon cross-coupled resistor, six-transistor SRAM cell design technique
US5196233A (en) * 1989-01-18 1993-03-23 Sgs-Thomson Microelectronics, Inc. Method for fabricating semiconductor circuits
US5106772A (en) * 1990-01-09 1992-04-21 Intel Corporation Method for improving the electrical erase characteristics of floating gate memory cells by immediately depositing a protective polysilicon layer following growth of the tunnel or gate oxide
US5151387A (en) 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
US5208168A (en) * 1990-11-26 1993-05-04 Motorola, Inc. Semiconductor device having punch-through protected buried contacts and method for making the same
US5187114A (en) * 1991-06-03 1993-02-16 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline P-channel load devices
US5204279A (en) * 1991-06-03 1993-04-20 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline p-channel load devices
US5241206A (en) * 1991-07-03 1993-08-31 Micron Technology, Inc. Self-aligned vertical intrinsic resistance
JP2750992B2 (ja) * 1992-08-12 1998-05-18 三菱電機株式会社 半導体装置およびその製造方法
US5384278A (en) * 1992-11-16 1995-01-24 United Technologies Corporation Tight control of resistor valves in a SRAM process
JP3404064B2 (ja) * 1993-03-09 2003-05-06 株式会社日立製作所 半導体装置及びその製造方法
US5506172A (en) * 1994-08-29 1996-04-09 Micron Technology, Inc. Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer
US6740573B2 (en) 1995-02-17 2004-05-25 Micron Technology, Inc. Method for forming an integrated circuit interconnect using a dual poly process
US5627103A (en) * 1995-03-02 1997-05-06 Sony Corporation Method of thin film transistor formation with split polysilicon deposition
US5587696A (en) * 1995-06-28 1996-12-24 Taiwan Semiconductor Manufacturing Company Ltd. High resistance polysilicon resistor for integrated circuits and method of fabrication thereof
US5751630A (en) * 1996-08-29 1998-05-12 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5699292A (en) * 1996-01-04 1997-12-16 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US5808941A (en) * 1996-01-04 1998-09-15 Micron Technology, Inc. SRAM cell employing substantially vertically elongated pull-up resistors
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers
JP2002359347A (ja) * 2001-03-28 2002-12-13 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP5567247B2 (ja) * 2006-02-07 2014-08-06 セイコーインスツル株式会社 半導体装置およびその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081481A (ja) * 1973-11-20 1975-07-02
JPS5132378U (ja) * 1974-09-02 1976-03-09
JPS52117580A (en) * 1976-03-30 1977-10-03 Fujitsu Ltd Manufacture for mis type integrating circuit
JPS5314580A (en) * 1976-07-26 1978-02-09 Hitachi Ltd Production of semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation
BE758160A (fr) * 1969-10-31 1971-04-01 Fairchild Camera Instr Co Structure metallique a couches multiples et procede de fabrication d'une telle structure
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices
US4016587A (en) * 1974-12-03 1977-04-05 International Business Machines Corporation Raised source and drain IGFET device and method
US3996657A (en) * 1974-12-30 1976-12-14 Intel Corporation Double polycrystalline silicon gate memory device
US4033026A (en) * 1975-12-16 1977-07-05 Intel Corporation High density/high speed MOS process and device
US4075045A (en) * 1976-02-09 1978-02-21 International Business Machines Corporation Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps
US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
US4052229A (en) * 1976-06-25 1977-10-04 Intel Corporation Process for preparing a substrate for mos devices of different thresholds

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081481A (ja) * 1973-11-20 1975-07-02
JPS5132378U (ja) * 1974-09-02 1976-03-09
JPS52117580A (en) * 1976-03-30 1977-10-03 Fujitsu Ltd Manufacture for mis type integrating circuit
JPS5314580A (en) * 1976-07-26 1978-02-09 Hitachi Ltd Production of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57115858A (en) * 1981-01-08 1982-07-19 Nec Corp Semiconductor device
JPS58501485A (ja) * 1981-09-14 1983-09-01 エヌ・シー・アール・インターナショナル・インコーポレイテッド 半導体基板の領域間に電気接触部を形成する方法
JPH058572B2 (ja) * 1981-09-14 1993-02-02 Ncr Co
JPS58130554A (ja) * 1982-01-28 1983-08-04 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
GB2017402B (en) 1982-05-26
DE2911132A1 (de) 1979-10-11
US4178674A (en) 1979-12-18
SG78884G (en) 1985-04-26
GB2017402A (en) 1979-10-03
HK14185A (en) 1985-03-08

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