JPS5349948A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5349948A
JPS5349948A JP12473576A JP12473576A JPS5349948A JP S5349948 A JPS5349948 A JP S5349948A JP 12473576 A JP12473576 A JP 12473576A JP 12473576 A JP12473576 A JP 12473576A JP S5349948 A JPS5349948 A JP S5349948A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit
ensure
low
mass productivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12473576A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12473576A priority Critical patent/JPS5349948A/en
Publication of JPS5349948A publication Critical patent/JPS5349948A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To ensure a low-cost mounting with an excellent mass productivity by connecting plural units of IC circuit to the circuit formed on the same insulator tape.
COPYRIGHT: (C)1978,JPO&Japio
JP12473576A 1976-10-18 1976-10-18 Semiconductor device Pending JPS5349948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12473576A JPS5349948A (en) 1976-10-18 1976-10-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12473576A JPS5349948A (en) 1976-10-18 1976-10-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5349948A true JPS5349948A (en) 1978-05-06

Family

ID=14892806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12473576A Pending JPS5349948A (en) 1976-10-18 1976-10-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5349948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5524477A (en) * 1978-08-09 1980-02-21 Nec Corp Integrated circuit
JPH02119153A (en) * 1988-06-01 1990-05-07 Hewlett Packard Co <Hp> Bonding method for integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5524477A (en) * 1978-08-09 1980-02-21 Nec Corp Integrated circuit
JPH02119153A (en) * 1988-06-01 1990-05-07 Hewlett Packard Co <Hp> Bonding method for integrated circuit

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