JPH11329923A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH11329923A
JPH11329923A JP10126945A JP12694598A JPH11329923A JP H11329923 A JPH11329923 A JP H11329923A JP 10126945 A JP10126945 A JP 10126945A JP 12694598 A JP12694598 A JP 12694598A JP H11329923 A JPH11329923 A JP H11329923A
Authority
JP
Japan
Prior art keywords
semiconductor
epitaxial layer
wafer alignment
alignment mark
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10126945A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11329923A5 (enExample
Inventor
Koichi Harada
耕一 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10126945A priority Critical patent/JPH11329923A/ja
Priority to EP99108764A priority patent/EP0961320A3/en
Priority to TW088107163A priority patent/TW432708B/zh
Priority to US09/306,727 priority patent/US6358814B1/en
Priority to KR1019990016707A priority patent/KR100610717B1/ko
Publication of JPH11329923A publication Critical patent/JPH11329923A/ja
Publication of JPH11329923A5 publication Critical patent/JPH11329923A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Solid State Image Pick-Up Elements (AREA)
JP10126945A 1998-05-11 1998-05-11 半導体装置の製造方法 Pending JPH11329923A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP10126945A JPH11329923A (ja) 1998-05-11 1998-05-11 半導体装置の製造方法
EP99108764A EP0961320A3 (en) 1998-05-11 1999-05-03 Semiconductor wafer comprising an epitaxial layer and an alignment mark
TW088107163A TW432708B (en) 1998-05-11 1999-05-03 Method for enhancing the alignment accuracy of semiconductor devices
US09/306,727 US6358814B1 (en) 1998-05-11 1999-05-07 Method for manufacturing semiconductor devices having an epitaxial layer and wafer alignment marks
KR1019990016707A KR100610717B1 (ko) 1998-05-11 1999-05-11 반도체 장치의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10126945A JPH11329923A (ja) 1998-05-11 1998-05-11 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPH11329923A true JPH11329923A (ja) 1999-11-30
JPH11329923A5 JPH11329923A5 (enExample) 2005-09-08

Family

ID=14947792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10126945A Pending JPH11329923A (ja) 1998-05-11 1998-05-11 半導体装置の製造方法

Country Status (5)

Country Link
US (1) US6358814B1 (enExample)
EP (1) EP0961320A3 (enExample)
JP (1) JPH11329923A (enExample)
KR (1) KR100610717B1 (enExample)
TW (1) TW432708B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019039173A1 (ja) * 2017-08-21 2019-02-28 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531374B2 (en) * 2001-08-10 2003-03-11 Taiwan Semiconductor Manufacturing Co., Ltd Overlay shift correction for the deposition of epitaxial silicon layer and post-epitaxial silicon layers in a semiconductor device
FR2869459B1 (fr) 2004-04-21 2006-08-04 Commissariat Energie Atomique Realignement entre niveaux apres une etape d'epitaxie.
CN113109997B (zh) * 2021-03-18 2022-08-26 上海信及光子集成技术有限公司 测量外延前后光刻套刻误差的方法及结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4632724A (en) * 1985-08-19 1986-12-30 International Business Machines Corporation Visibility enhancement of first order alignment marks
US4936930A (en) * 1988-01-06 1990-06-26 Siliconix Incorporated Method for improved alignment for semiconductor devices with buried layers
JPH0291690A (ja) * 1988-09-28 1990-03-30 Toshiba Corp 拡大縮小表示方式
JPH0478123A (ja) * 1990-07-20 1992-03-12 Fujitsu Ltd 半導体装置の製造方法
US5300797A (en) * 1992-03-31 1994-04-05 Sgs-Thomson Microelectronics, Inc. Coplanar twin-well integrated circuit structure
JPH05343319A (ja) * 1992-06-09 1993-12-24 Sumitomo Electric Ind Ltd 半導体装置の製造方法
JPH07130603A (ja) * 1993-06-24 1995-05-19 Hitachi Ltd 半導体装置の製造方法
KR0170909B1 (ko) * 1995-09-27 1999-03-30 김주용 반도체 소자의 오버레이 검사방법
JPH09181189A (ja) * 1995-12-25 1997-07-11 Toshiba Corp 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019039173A1 (ja) * 2017-08-21 2019-02-28 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法
US11329002B2 (en) 2017-08-21 2022-05-10 Sony Semiconductor Solutions Corporation Semiconductor device and fabrication method for semiconductor device

Also Published As

Publication number Publication date
EP0961320A3 (en) 2001-01-17
TW432708B (en) 2001-05-01
US6358814B1 (en) 2002-03-19
EP0961320A2 (en) 1999-12-01
KR100610717B1 (ko) 2006-08-09
KR19990088170A (ko) 1999-12-27

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