JPH10510953A - 製造に適した、低誘電性、低配線抵抗かつ高性能icを達成するための新規なプロセス技術 - Google Patents
製造に適した、低誘電性、低配線抵抗かつ高性能icを達成するための新規なプロセス技術Info
- Publication number
- JPH10510953A JPH10510953A JP8519801A JP51980196A JPH10510953A JP H10510953 A JPH10510953 A JP H10510953A JP 8519801 A JP8519801 A JP 8519801A JP 51980196 A JP51980196 A JP 51980196A JP H10510953 A JPH10510953 A JP H10510953A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/10—Lift-off masking
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/95—Multilayer mask including nonradiation sensitive layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/951—Lift-off
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.それぞれソースコンタクトおよびトルインコンタクトによって接触されるソ ース領域およびドレイン領域を含んだウェハ上に形成され、ソース領域およびド レイン領域の各々はゲート電極によって接触されるゲート領域によって分離され 、第1のレベルのパターニングされた配線は所望のパターンで前記ソースコンタ クト、前記ドレインコンタクトおよび前記ゲート電極に接触し、第2のレベルの パターニングされた配線(18)は複数個の金属線(14)によって前記第1の レベルのパターニングされた配線に接触する半導体装置(10)であって、前記 金属線(14)は第1の誘電材料(12)によって分離され、前記第2のレベル のパターニングされた配線(18)は低抵抗金属を含み、前記低抵抗金属の拡散 に対して不活性の平坦化された誘電材料(20)によって分離される、半導体装 置。 2.前記低抵抗金属(18)は約2.8μΩ−cm未満のシート抵抗を有する、 請求項1に記載の半導体装置。 3.前記低抵抗金属(18)はおおよそ2,000Åから10,000Åの範囲 内の厚さを有する、請求項2に記載の半導体装置。 4.前記低抵抗金属(18)の下に高融点金属の薄い層をさらに含み、前記薄い 層はおおよそ200Åから300Åの範囲内の厚さを有する、請求項3に記載の 半導体装置。 5.前記平坦化された誘電材料(20)はベンゾシクロブテンまたはその派生物 から本質的になる、請求項1に記載の半導体装置。 6.前記平坦化された誘電材料(20)はおおよそ4,000Åから10,00 0Åの範囲内の厚さを有する、請求項5に記載の半導体装置。 7.請求項1の半導体装置を作製するためのプロセスであって、前記第2のレベ ルのパターニングされた配線を形成するステップを含み、前記ステップは、 (a) 前記第1のレベル間誘電体層(12)上に3層レジスト(16)を形 成し、パターニングして、前記金属線(14)の上部部分を露出するステップを 含み、前記3層レジスト(16)は、溶解可能なポリマーの第1の層(16a) と、ハードマスク材料の第2の層(16b)と、レジスト材料の第3の層(16 c)とを含み、さらに、 (b) 前記ウェハ上に前記低抵抗金属層(18)をブラケット堆積するステ ップと、 (c) 前記溶解可能なポリマーの前記第1の層(16a)を除去してその上 の金属(18)をリフトオフするステップと、 (d) 前記金属層(18)を覆うために、前記誘電材料のコーティングをス ピンオンして前記平坦化された誘電材料(20)を形成するステップとを含む、 プロセス。 8.前記溶解可能なポリマー(16a)はおおよそ0.5μmから3μmの範囲 内の厚さに形成される、請求項7に記載の方法。 9.前記ハードマスク材料(16b)は、SiO2、シリコンオキシナイトライ ド、スパッタリングされたシリコン、アモルファスシリコン、およびアモルファ ス炭素からなるグループから選択される材料を含み、前記ハードマスク材料(1 6b)はおおよそ200Åから500Åの範囲内の厚さに形成される、請求項7 に記載の方法。 10.前記レジスト材料(16c)は5,000Åから15,000Åの範囲内 の厚さに形成される、請求項7に記載の方法。 11.前記金属層(18)は第1の温度で堆積され、前記溶解可能なポリマー( 16a)は前記第1の温度よりも高いガラス転移温度を有し、前記ウェハは、前 記第1の温度よりも高いが前記ガラス転移温度よりも低い温度でベーキングされ 、前記ベーキングは前記溶解可能なポリマー(16a)のレジストパターン規定 およびエッチングに続いて行なわれる、請求項7に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/360,856 | 1994-12-21 | ||
US08/360,856 US5550405A (en) | 1994-12-21 | 1994-12-21 | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
PCT/US1995/015251 WO1996019830A1 (en) | 1994-12-21 | 1995-11-22 | Novel processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ic |
Publications (1)
Publication Number | Publication Date |
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JPH10510953A true JPH10510953A (ja) | 1998-10-20 |
Family
ID=23419674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8519801A Ceased JPH10510953A (ja) | 1994-12-21 | 1995-11-22 | 製造に適した、低誘電性、低配線抵抗かつ高性能icを達成するための新規なプロセス技術 |
Country Status (7)
Country | Link |
---|---|
US (3) | US5550405A (ja) |
EP (1) | EP0799497B1 (ja) |
JP (1) | JPH10510953A (ja) |
KR (1) | KR100383392B1 (ja) |
DE (1) | DE69514686T2 (ja) |
TW (1) | TW301043B (ja) |
WO (1) | WO1996019830A1 (ja) |
Cited By (2)
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JP2010532817A (ja) * | 2007-04-03 | 2010-10-14 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | 局所皮膜の堆積方法 |
US8344379B2 (en) | 2005-11-17 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method of the same |
Families Citing this family (119)
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DE69514686T2 (de) | 2000-08-31 |
EP0799497B1 (en) | 2000-01-19 |
WO1996019830A1 (en) | 1996-06-27 |
US5965934A (en) | 1999-10-12 |
DE69514686D1 (de) | 2000-02-24 |
KR100383392B1 (ko) | 2003-07-18 |
KR980700690A (ko) | 1998-03-30 |
EP0799497A1 (en) | 1997-10-08 |
US5679608A (en) | 1997-10-21 |
US5550405A (en) | 1996-08-27 |
TW301043B (ja) | 1997-03-21 |
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