TW494534B - Method of fabricating a dual damascene structure - Google Patents

Abstract

A conducting layer is formed on a substrate and a first passivation layer is formed on the conducting layer. Following this, a first photo-chemical low dielectric constant (low-k) layer, a second passivation layer and a second low-k photo-chemical layer are formed in order on the substrate. Then, a first photolithographic process is performed to form a trench in the second low-k photo-chemical dielectric layer. A first etching process is performed to remove portions of the second passivation layer not covered by the second low-k photo-chemical layer down to the surface of the first low-k photo-chemical layer. Subsequently, a second photolithographic process is performed to form a via hole in the first low-k photo-chemical layer. Finally, a second etching process is performed to remove portions of the first passivation layer not covered by the first low-k photo-chemical layer down to the surface of the conducting layer.

Description

494534 V. Description of the invention (1) Field of the invention The present invention provides a method for making a dua 1 damascene structure, especially a photo-chemical that uses a low-k dielectric. material) method of making a dual-mosaic structure 'to simplify the dual-town post-production process. Background Description The dual damascene process is a method capable of simultaneously forming a metal wire and a plug (p 1 ug) stacked structure above and below the dielectric layer. The dual damascene structure mainly includes an upper trench and a lower contact. A via hole is used to connect different elements and wires' between the layers in the semiconductor wafer and isolate the other elements from each other by using the inner layer dielectric materials surrounding them. With the development of integrated circuits becoming more sophisticated and complex, how to effectively reduce the complexity and production cost of the dual-mosaic structure before the yield is an important issue in the current integrated circuit manufacturing process. Please refer to FIGS. 1 to 7, which are schematic diagrams of a conventional method for making a double mosaic structure. As shown in FIG. 1, the semiconductor wafer includes a substrate 12, a conductive layer η is provided in a predetermined region of the surface of the substrate 2, and the surface of the conductive layer 14 is covered with a nitride nitride (siiic 〇n ni tr ide) 16. Since the base 丨 2 other components of the surface layer

It is not the focus of the dual damascene process. Therefore, other components are not shown in Figure 1 and shown in the figure. It is shown that the surface of the substrate 12 and the surface of the body wafer 10 further include a low dielectric constant. In addition, a passivation layer 20, a low dielectric layer: a bucket layer 丨 8, a protective layer hard cover curtain layer 24 are sequentially stacked on the protective layer -16 surface ... a material layer 22 and a low dielectric layer Constant material layers 18 and 22-早早 i # ⑼ 么 士 (spin-on-coating) low dielectric constant material is made of steel and cloth, and is used to form a double mosaic junction ^ FLARETW ,,, Fuye reduced the RC de-ay effect between the wires. Because of the low dielectric constant | ^ ^ ^ ^ ^ ^ dielectric constant material) has easy brittleness (I it is a gate organic low dielectric

& human ^, ag 1 1 e), so it must be heated, the material layer 18 surface t is covered with mr composed of a more dense material, such as gasification ί !, in order to increase the low dielectric constant material layer In the same way as above, the surface of the low Π constant material layer 22 is also covered with a -preservation layer, that is, the hard mask layer 24 used as a subsequent etching mask. The hard mask layer 24 is composed of silicon nitride or silicon oxynitride (siHeQn 0 SiON). ae, as shown in FIG. 2, a pattern of trenches on the upper surface of the low-dielectric-constant material layer 18 is formed on the surface of the low-dielectric-constant material layer 18, which is then subjected to a lithography and etching process. Subsequently, a photoresist layer 26 is coated on the surface of 10, and a stackable structure shown in FIG. 1 is formed in 26 to reach a low dielectric constant. Then, a hardened curtain layer 24 is formed to form a reachable opening σ 2 5 To define a double damascene junction, as shown in FIG. 3, another lithography process is performed on the semiconductor wafer to open the surface 27 of the photoresist layer layer 2 2 surface. by

Page 6 494534 V. Description of the invention (3) The opening 27 is used to define a lower contact hole of a double mosaic structure. Therefore, the width of the opening 27 must be smaller than the width of the opening 25, and it is placed inside the opening 25. In order to facilitate the subsequent use of a self-aligned contact etching process to form a dual damascene as shown in Figure 4, and then perform a first etching process, an anisotropic dry etch process, along the; The low dielectric constant material and the protective layer 20 that are not covered by the photoresist layer 26 are removed vertically downward to form an opening 28 that reaches the low dielectric constant material layer. Then, a photoresist stripping process is performed to completely remove the photoresist layer 26. As shown in FIG. 5, a second etching process is performed next, and the layer 20 and the protective layer 16 serve as stop iayer, and the low-dielectric-constant material layer 22 and the low-k material layer covered by the hard mask layer 24 After the material layer 18 ′, the protection layer 16 which is not covered by the hard cover curtain layer 2 4 is removed, so as to form a double-inlaid structure upper trench 3 penetrating the low dielectric constant material bucket protective layer 20 at the same time. 〇, and a self-alignment on the upper side to form a lower contact hole 3 i of the dual damascene structure penetrating the surface of the low dielectric constant material layer 18 and the surface of the conductive layer 14. As shown in FIG. 6, a deposition process is then performed to form a barrier layer 32 on the semiconductor surface. The barrier layer 3 2 is composed of silicon nitride to avoid the copper (Cu) or cast pattern constituting the conductive layer 14, and the ports 2 7 are structured. Such as a non-uniform opening 2 7 material layer 2 2 to 18 surface use to remove the non-dielectric constant when the protection layer 20 to layer 2 2 and the protection groove 30 under the protective layer 1 6 straight wafer 10 0, metal can be used

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V. Description of the invention (4) (tungsten, W) diffuses into silicon, is composed of composite materials such as 戍 (丁 3 / 了 丨 / 1 ^^ 〇, etc.), and is divided into two groups: titanium / titanium / titanium nitride The conductive layer and the double-layered private mask are used to increase subsequent coverage by performing a dry etch to remove the adhesion between the conductive structure and the substrate 32. After that, the surface of the conductive layer 14 is exposed to the surface of the surface. A part of the barrier layer forms a conductive layer 34 and makes it conductive; and then a contact hole 31 is formed on the barrier layer 32. 3 4 is filled with the upper trench 30 and the bottom as shown in FIG. Chemical mechanical polishing process, using the barrier layer 32 as an end-polnt to remove the cover on the upper layer

30 and the conductive layer in the area other than the lower contact hole 31 so that the surface of the upper layer trench 30 and the conductive layer 34 in the lower contact hole 31 are approximately tangent to the surface of the barrier layer 32 outside the upper acoustic groove 30 . Finally, a protective layer 36, such as a silicon nitride layer, is formed on the surface of the semiconductor crystal to complete the fabrication of the dual damascene. 、、 口 '/ Because of the conventional dual-damascene process, the semiconductor wafer 10 is first placed in a lithographic device for exposure and development to define the pattern of the upper trench 30 and the lower contact hole 31, and then follow The defined pattern is engraved to form structures such as an upper trench 30 and a lower contact hole 31. However, with the increase of the element accumulation, the aspect ratio of the upper trench 30 and the lower contact hole 31 also increases. When the process window is limited, light is used. When defining a pattern, it will be subject to the resolution limit (res〇luti〇n of the optical exposure tool)

Page 8 494534 V. Description of the invention (5) 1 imit) restrictions, and the upper groove 30 and the lower contact hole 3 1 # # are also easy to affect the contour of the component during the engraving process, which further increases the difficulty of the dual damascene process. degree. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for forming a dual damascene structure on the surface of a semiconductor wafer to improve the resolution of the dual damascene structure. Another object of the present invention is to provide a method for forming a dual damascene structure on the surface of a semiconductor wafer to simplify the dual damascene process and reduce production costs. In a preferred embodiment of the present invention, a conductive layer is formed before the substrate surface of a semiconductor wafer, and a first protective layer is formed on the surface of the conductive layer. Then, a first photo-chemical low dielectric constant material layer, a second protective layer, and a second photochemical low dielectric constant material layer are sequentially formed on the surface of the semiconductor wafer and covered on the semiconductor wafer surface. On the conductive layer. Then, a first lithography process is performed to form an upper trench of the dual damascene structure in the second photochemical low dielectric constant material layer. Then, a first etching process is performed to etch a second protective layer that is not covered by the second photochemical low-dielectric constant material layer until the surface of the first photochemical low-dielectric constant material layer. A second lithography process is then performed to form one of the dual damascene structures in the first photochemical low-dielectric constant material layer.

494534 V. Description of the invention (6) The lower contact hole. Finally, a second remaining process is performed, and the first protective layer that is not covered by the first photochemical low-dielectric constant material layer is left to the surface of the conductive layer to complete the fabrication of the dual damascene structure. Since the present invention uses a photochemical low dielectric constant material to make a dual damascene structure, the photochemical material can provide excellent resolution, and is particularly suitable for components of 0.1 3 microns (micrometer, // m) or smaller Therefore, the quality of the lithography process can be effectively improved, and when photochemical materials are used to form the upper-layer trenches and lower contact holes of the dual damascene structure, only the conventional exposure and development processes are required, that is, the photochemical material layer can be used. Forming the upper-layer trench and the lower-layer contact hole, thereby avoiding problems that may be derived from the conventional etching process for forming the upper-layer trench and the lower-layer contact hole. In other words, the invention can not only improve the electrical performance of the dual damascene structure, improve the yield of the dual damascene process, but also effectively simplify the dual damascene process and reduce production costs. Detailed description of the invention Please refer to FIGS. 8 to 13. FIGS. 8 to 13 are schematic diagrams of a method for fabricating a dual damascene structure on a surface of a semiconductor wafer 40 according to the first embodiment of the present invention. A first embodiment of the present invention discloses a trench-first dual damascene process. As shown in FIG. 8, the semiconductor wafer 40 includes a substrate 42, a conductive layer 44 is provided in a predetermined area of the surface layer of the substrate 42, and a protective layer 46 is provided on the surface of the conductive layer 44. The conductive layer 4 4 is a copper wire, and the protective layer 4 6 is made of silicon nitride, silicon oxynitride, or silicon nitride.

Page 10 494534, Description of the invention (7) It is composed of silicon carbon. In the cone of the present invention, the surface of the semiconductor wafer 40 further includes a photochemical low dielectric layer 48, a protective layer 50, and another photochemical low dielectric constant. Two == sequentially stacked on the surface of the protective layer 46. Yanshi is placed in the photochemical low dielectric: = 2 The protective layer 50 between 48 and 52 is mainly used as the # etch stop layer when defining the upper trench ^ ^ 2 In order to simplify the process, Second, J rounds 0 by omitting 'and defining the upper trench by the control of the etching time point'. In the preferred embodiment of the present invention, the photochemical low dielectric constants 48 and 52 are both composed of the stable magnesium compounds. (Magnesia stabiiiz ^ MS, Z), and spin coating is used on the semiconductor wafer 40. In other embodiments, the actinic, dielectric constant material layers 48 and 52 may also be composed of a stabilized zirconium yttrium compound (stabilized zirconia, YSZ) or other photosensitive material. The protective layer 50 is made of fluorosilicate glass ( FSG). In addition, silicon nitride, silicon oxynitride, or silicon carbide can also be used as the material of the protective layer 50. As shown in FIG. 29, a first photolithography process is then performed to form a double damascene structure upper trench 5 3 in the photochemical low-k constant material layer 5 2. The photochemical low-intermediate human material layer composed of the oxide town (Mg0) and zirconia (Zr〇2) is not only a kind of photoactivity, but also has a high degree of hardness. And good heat resistance (thermal Sh0ck resistance), so the first lithography process

Page 11 V. Description of the invention (8) ~~-f = That is, there is no need to cover the surface with a masking layer and a photoresist layer before the photochemical low-dielectric constant material layer 5 2; The electric constant = the pattern of the upper trench 5 3 is defined on the j layer 5 2 to simplify the process flow and save f ^ process time and cost. When performing the first lithography process, it is in accordance with the general lithography process, including pre-baking at 90 ° C for about one minute, and then using an electron beam (eiectr〇rl beam). , EB) or ultraviolet (ultraviolet, uv) exposure, and using tetramethyl ammonium hydroxide (TMAH) as a developing solution for the development process, and finally at 150 ° C environment Hard bake in about minutes. The photochemical low-dielectric constant material layer 52 processed as described above can generate Si-0 and Si-CH bonding, so that the photochemical low-dielectric constant material layer 52 has a low dielectric constant of about 2 · 7 and a good Abrasion resistance. As shown in FIG. 10, a first etching process is then performed, using the photochemical low 4 > electric constant material layer 5 2 as an etching mask, and removing the protective layer 50 vertically along the upper trench 5 3 so that The surface of the photochemical low dielectric constant material layer 48 under the upper trench 53 is exposed. As shown in FIG. 11, a second lithography process is subsequently performed to form a lower contact hole 54 of a dual damascene structure in the photochemical low dielectric constant material layer 48. The steps of the second lithography process are similar to the aforementioned first lithography process. These steps include (1) pre-bake for about one minute under 90 ° C ring, and then Use electron beam (EB) or ultraviolet light (UV) for exposure, (2) use tetramethylammonium hydroxide (TM AH) as a developing solution for developing process, (3) enter at 150 ° C environment

Page 12 494534 V. Description of the invention (9) Hard roast for about one minute. Similarly, in order to connect the lower contact hole 54 to the surface of the conductive layer 44, a second etching process is performed to remove the protective layer 46 which is not covered by the photochemical low dielectric constant material layer 48.

Then, as shown in FIG. 12, a deposition process is performed to form a barrier layer 56 on the surface of the semiconductor wafer 40. The barrier layer 56 may be composed of silicon nitride to prevent the copper metal constituting the conductive layer 44 from diffusing into the silicon. The barrier layer 56 can also be composed of a composite material such as silicon nitride and tantalum / titanium / titanium nitride (13/1 ^ / 1 ^ 趵), so as to increase the subsequent conductive layer and double layer covering the dual damascene structure. Adhesion between the mosaic structures. A dry etch is then performed to remove a portion of the barrier layer 56 covering the surface of the conductive layer 44, so that the surface of the conductive layer 44 is exposed. Then on the surface of the barrier layer 56 A conductive layer 58 is formed, such as a copper metal layer, and the conductive layer 5 8 fills the upper trench 5 3 and the lower contact hole 54. In addition, in other embodiments of the present invention, the conductive layer 58 can also be formed by The other metal layers are formed to form a metal interconnection with a dual damascene structure.

As shown in FIG. 13, a metal chemical mechanical polishing process is subsequently performed, and the barrier layer 56 is used as the polishing end point to remove the conductive layer 5 8 covering the area other than the upper trench 5 3 and the lower contact hole 5 4, and The surface of the conductive layer 5 8 remaining in the upper-layer trench 5 3 and the lower-layer contact hole 54 is approximately tangent to the surface of the barrier layer 5 6 outside the upper-layer trench 5 3. Finally, a protective layer 60, such as a silicon nitride layer, is formed on the surface of the semiconductor wafer 40 to complete the dual damascene structure.

Page 13 494534 V. Description of the invention (ίο) Since the present invention uses a photochemical low dielectric constant material to make a dual mosaic structure, the photochemical material can provide excellent resolution, so it can effectively improve the quality of the lithography process. Moreover, when using photochemical materials to form the upper-layer trenches and lower-level contact holes of the dual damascene structure, only the conventional .exposure and development processes are required to form upper-layer trenches and lower-level contact holes in the photochemical material layer, thereby avoiding It is known that the yellow light and etching process of the upper trench and the lower contact hole need to be formed by using an additional photoresist layer.

Please refer to FIG. 14 to FIG. 17, which are schematic diagrams of a method for fabricating a dual damascene structure on a surface of a semiconductor wafer 70 according to a second embodiment of the present invention. The second embodiment of the present invention discloses a via-first dual damascene process. As shown in FIG. 14, the semiconductor wafer 70 includes a substrate 72, a conductive layer 74 is provided in a predetermined area of the surface layer of the substrate 72, and a protective layer 76 is provided on the surface of the conductive layer 74. In addition, the surface of the semiconductor wafer 70 further includes a photochemical low dielectric constant material layer 78, a protective layer 80, and another photochemical low dielectric constant material layer 82, which are sequentially stacked on the surface of the protective layer 76. The protective layer 80 provided between the photochemical low-dielectric constant material layers 7 8 and 8 2 can be omitted, and only the control of the etching time is used to define the contour of the upper trench of the dual damascene structure to simplify the process.

After the above-mentioned stacked structure is formed, as shown in FIG. 14, a first lithography process is performed to form an opening 8 3 in the photochemical low-dielectric constant material layer 82. The opening 8 3 is used for Defines the pattern of the underlying contact hole. after that

Page 14 494534 V. Description of the invention (11) Perform a first etching process, using the photochemical low dielectric constant material layer 8 2 as an etching mask, and remove the protective layer 80 vertically downward along the opening 8 3 so that The surface of the photochemical low-dielectric constant material layer 78 under the opening 83 is exposed, and the pattern of the lower contact hole is transferred to the protective layer 80. As shown in FIG. 15, a second lithography process is subsequently performed to form a dual damascene structure upper trench 8 4 in the photochemical low-dielectric constant material layer 8 2, and simultaneously transfer the lower contact in the protective layer 80. The hole pattern is inserted into the photochemical low-dielectric constant material layer 78 to form a lower-layer contact hole 85. Then, as shown in FIG. 16, a second etching process is performed to remove the protective layer 76, which is not covered by the photochemical low-dielectric constant material layer 78, so that the lower contact hole 85 is connected to the surface of the conductive layer 74. As shown in FIG. 17, the surface of the dual damascene structure and the surrounding photochemical low dielectric constant material layer 8 2 is subsequently covered with a barrier layer 86, and the lower layer is contacted with the surface of the conductive layer 74 below the hole 85. Exposed. Then, a conductive layer 8 8 is filled in the upper trenches 8 4 and the lower contact holes 8 5 of the dual damascene structure, and the conductive layer 8 8 is polished by a chemical mechanical polishing process, so that the conductive layer 8 in the upper trenches 84 is filled. The 8 surface is cut to the surface of the barrier layer 86 outside the upper trench 8 4. Finally, a protective layer 90 is formed on the surface of the semiconductor wafer 70 to complete the fabrication of the dual damascene structure.

As the contact hole priority dual damascene process must use a phase-in pattern transfer method, the pattern of the lower contact hole is used to form the shape.

Page 15 494534 V. Description of the invention (12) The dielectric layer forming the upper trench is transferred downward to the dielectric layer used to form the lower contact hole, and the present invention uses a photochemical low dielectric constant material to make a dual damascene. The structure can effectively simplify the production process, that is, because the photochemical materials, such as YSZ and MSZ, have photosensitive properties, the present invention can omit the conventional extra-etching process used to form the upper trench and the lower contact hole contour. Compared with the conventional dual-damascene process, the present invention uses a photochemical low-dielectric constant material to make a dual-damascene structure. Photochemical materials, such as YSZ and MSZ, can provide excellent resolution and can effectively improve lithography. The quality of the process is especially suitable for the process of components of 0 · 13 microns or smaller. Moreover, when photochemical materials are used to form the upper-layer trenches and lower-layer contact holes of the dual damascene structure, only the conventional exposure and development processes are required, that is, the upper-layer trenches and lower-layer contact holes can be formed in the photochemical material layer, thereby avoiding the habit It is known that the yellow light of the upper trench and the lower contact hole using the organic photoresist layer and the etching process may cause problems. In other words, the invention can not only improve the electrical performance of the dual damascene structure, improve the yield of the dual damascene process, but also simplify the dual damascene process and reduce production costs. The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention should be covered by the present invention patent.

Page 16 494534 Simple explanation of the diagrams Simple explanation of the diagrams Figures 1 to 7 are schematic diagrams of the conventional method for making a double mosaic structure. FIGS. 8 to 13 are schematic diagrams of a method for fabricating a dual damascene structure on a semiconductor wafer surface according to the first embodiment of the present invention. 14 to 17 are schematic diagrams of a method for fabricating a dual damascene structure on a semiconductor wafer surface according to a second embodiment of the present invention. Explanation of symbols in the figure 10 Semiconductor wafer 12 Base 14 Conductive layer 16> 20 ^ 36 Protective layer 18 ^ 22 Low dielectric constant material layer 24 Hard cover curtain layer 25 ^ 2Ί, 28 U 26 Photoresist layer 30 Upper trench 31 Lower contact hole 32 Barrier layer 34 Conductive layer 40 Semiconductor wafer 42 Substrate 44 Conductive layer 46> 50 '60 Protective layer 48 ^ 52 Photochemical low dielectric constant material layer 53 Upper trench 54 Lower contact hole 56 Barrier layer 58 Conductive Layer 70 semiconductor wafer 72 substrate

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Claims (1)

494534 VI. Application Patent Scope 1. A method for making a dual damascene structure on the surface of a semiconductor wafer, the semiconductor wafer includes a substrate and a conductive layer provided on the substrate, and the surface of the conductive layer A first protective layer is formed, and the method includes the following steps: A first photo-chemical low dielectric constant material layer and a second protective layer are sequentially formed on the surface of the semiconductor wafer. And a second photochemical low-dielectric constant material layer covering the conductive layer; A first photolithography process is performed to form an upper trench of the dual damascene structure in the second photochemical low dielectric constant material layer; a first et ch process is performed, and the etching is not performed. The second protective layer covered by the second photochemical low-dielectric constant material layer up to the surface of the first photochemical low-dielectric constant material layer; performing a second lithography process for the first photochemical low-dielectric constant material Forming a lower contact hole (via ho 1 e) of the dual damascene structure in the electric constant material layer; and performing a second etching process to etch the first uncovered first photochemical low dielectric constant material layer The protective layer is up to the surface of the conductive layer to complete the fabrication of the dual mosaic structure. 2. The method according to item 1 of the patent application, wherein the first photochemical low-dielectric constant material layer and the second photochemical low-dielectric constant material layer are made of MSZ (magnesia stabilized zirconia) or YSZ (yttria Page 19 494534 VI. Patent scope stabilized zirconia). 3. The method according to item 1 of the patent application scope, wherein the first protective layer is composed of silicon nitride, silicon-oxy-nitride, or silicon carbon. 4. The method according to item 1 of the patent application, wherein the second protective layer is made of fluorspar glass (FSG), silicon nitride, silicon-oxy-nitride, or carbonized stone (silicon carbon). 5. The method of claim 1 in which the conductive layer is a copper wire. 6. A method for fabricating a double damascene structure on a semiconductor wafer surface, the semiconductor wafer includes a substrate and a conductive layer provided on the substrate, and a first protective layer is formed on the surface of the conductive layer, the method includes the following steps : A first photochemical low-dielectric constant material layer, a second protective layer, and a second photochemical low-dielectric constant material layer are sequentially formed on the surface of the semiconductor wafer and cover the conductive layer; A lithography process to form a pattern of a lower contact hole of one of the dual damascene structures in the second photochemical low dielectric constant material layer; Page 20 494534 6. The scope of the patent application is to perform a first etching (et ch) process to etch the second protective layer that is not covered by the second photochemical low-dielectric constant material layer until the first photochemical low-dielectric The surface of the dielectric constant material layer to transfer the pattern of the lower contact hole in the second photochemical low-dielectric constant material layer to the second protective layer; perform a second lithography process for the second photochemical An upper trench of the dual damascene structure is formed in the low dielectric constant material layer, and the pattern of the lower contact hole in the second protective layer is transferred to the first photochemical low dielectric constant material layer to form the lower layer. Contact holes; and A second etching process is performed to etch the first protective layer not covered by the first photochemical low-dielectric constant material layer to the surface of the conductive layer to complete the fabrication of the dual damascene structure. 7. The method of claim 6 in which the conductive layer is a copper wire. 8. The method of claim 6 in which the first protection layer is composed of silicon nitride, silicon oxynitride, or silicon carbide. 9. The method according to item 6 of the patent application, wherein the second protective layer is composed of fluorosilicon glass (FSG), silicon nitride, silicon oxynitride, or silicon carbide. 10. The method according to item 6 of the application, wherein the first photochemical low-dielectric constant material layer and the second photochemical low-dielectric constant material layer are composed of MSZ or YSZ. Page 21