JPH1022338A - フリップチップ接続方法 - Google Patents

フリップチップ接続方法

Info

Publication number
JPH1022338A
JPH1022338A JP8174582A JP17458296A JPH1022338A JP H1022338 A JPH1022338 A JP H1022338A JP 8174582 A JP8174582 A JP 8174582A JP 17458296 A JP17458296 A JP 17458296A JP H1022338 A JPH1022338 A JP H1022338A
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
adhesive
bump electrodes
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8174582A
Other languages
English (en)
Inventor
Toyoki Asada
豊樹 浅田
Naoya Isada
尚哉 諌田
Yasuhiro Narukawa
泰弘 成川
Yoshio Ozeki
良雄 大関
Tetsuo Tajima
哲夫 田島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8174582A priority Critical patent/JPH1022338A/ja
Publication of JPH1022338A publication Critical patent/JPH1022338A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract

(57)【要約】 【課題】フリップチップ接続方法において、簡単でかつ
短時間な組立工程により、組立コストを低減し、更に高
信頼性を得るフリップチップ接続方法を提供する。 【解決手段】半導体チップ３のバンプ電極２を有する面
と基板５の配線４を有する面に、二液型接着剤１を塗付
し、半導体チップ３のバンプ電極２と基板５と配線４を
位置合わせした後、半導体チップ３を基板５上に搭載す
る。この時、二液型接着剤１は短時間で硬化し、半導体
チップ３のバンプ電極２と基板５と配線４は電気的に接
続され、接続状態が保持できる。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は電子回路部品等の実
装技術に関する。
【０００２】
【従来の技術】従来、フリップチップ接続方法では、多
種多様に接着剤が用いられている。その一例として、例
えば特公平６−１０５７２７号公報に開示されているも
のがある。この公報で用いられる接着剤はアクリル、エ
ポキシ系を主成分とし、光硬化、熱硬化併用型あるいは
熱硬化型で、更に硬化時には、硬化時に発生する収縮力
が高温での絶縁抵抗の熱応力よりも大きくなるようなも
のである。この公報のフリップチップ接続方法は、接着
剤を、配線を有する有機、セラミック等の基板に塗布
し、半導体チップのバンプ電極と基板配線を位置合わせ
した後、半導体チップを基板上に搭載し、加圧ツールに
より加圧し、その加圧状態のまま、接着剤を、熱、また
は光を与えて、接着剤を硬化させる方法である。
【０００３】
【発明が解決しようとする課題】しかし、上記に記載し
たフリップチップ接続方法には下記の問題があった。接
着剤を硬化する時に加圧ツール、および加圧治具で押さ
えながら、熱、または光によって硬化する必要がある。
そのため、組立工程は複雑になり、組立コストを高価に
するという問題があった。
【０００４】本発明の目的は、フリップチップ接続の組
立コストの問題点を解決し、更に、高信頼性を得るフリ
ップチップ接続方法を提供するものである。
【０００５】
【課題を解決するための手段】本発明は、上記目的を達
成するために、フリップチップ接続方法において、二液
型接着剤を用いた。二液型接着剤を半導体チップのバン
プ電極を有する面と基板の配線を有する面に塗布し、半
導体チップのバンプ電極と基板配線を位置合わせした
後、半導体チップを基板上に搭載させる。この時、半導
体チップと基板に塗布した二液型接着剤は短時間で硬化
し、半導体チップのバンプ電極と基板配線を電気的に接
続させ、更に接続状態を保持できる方法である。
【０００６】
【発明の実施の形態】
（実施例１）本発明の実施例を図１、図２に示す。
【０００７】まず図１に示すように、半導体チップ３の
バンプ電極２を有する面と基板５の配線４を有する面
に、二液型接着剤１をディスペンサ６により塗付する。
二液型接着剤１は、例えば、エポキシ系、シリコン系の
接着剤を用いる。
【０００８】次に図２に示すように、半導体チップ３を
反転させ、半導体チップ３のバンプ電極２と基板５、配
線４を位置合わせした後、半導体チップ３と基板５のそ
れぞれに塗布した二液型接着剤１を張り合わさるよう
に、半導体チップ３を基板５上に搭載する。この時、半
導体チップ３と基板５のそれぞれに塗付された二液型接
着剤１は混合され、１０分で硬化し、バンプ電極２と基
板５、配線４は電気的に接続され、更に接続状態を保持
できる。
【０００９】（実施例２）本発明の実施例を図３、図４
に示す。基板は有機基板１６を用いた場合で、以下に説
明する。
【００１０】まず図３に示すように、半導体チップ１３
のバンプ電極１２を有する面と有機基板１６の配線１５
を有する面に、二液型接着剤をディスペンサ１７により
塗付する。二液型接着剤は、硬化後半導体チップ１３の
弾性率と同指数の弾性率をもつ堅い接着剤１１、例えば
アクリル系の瞬間接着剤と硬化後有機基板１６と同指数
の弾性率をもつ柔らかい接着剤１４、例えば、硬化後ゴ
ム状のシリコン系弾性接着剤を用いる。二液型接着剤を
半導体チップ１３側には、硬化後半導体チップ１３の弾
性率と同指数の弾性率をもつ堅い接着剤１１を半導体チ
ップ１３のほぼ中央に塗布し、有機基板１６には、硬化
後有機基板１６と同指数の弾性率をもつ柔らかい接着剤
１４を有機基板１６のほぼ中央付近に塗付する。
【００１１】次に図４に示すように、半導体チップ１３
を反転させ、半導体チップ１３のバンプ電極１２と有機
基板１６の配線１５を位置合わせした後、半導体チップ
１３と有機基板１６のそれぞれに塗布した二液型接着剤
を張り合わさるように、半導体チップ１３を有機基板１
６上に搭載する。この時、半導体チップ１３に塗付され
た硬化後半導体チップ１３と同指数の弾性率をもつ堅い
接着剤１１と、有機基板１６に塗付された硬化後有機基
板１６と同指数の弾性率をもつ柔らかい接着剤１４は混
合され、１０分で硬化し、バンプ電極１２と配線１５は
電気的に接続され、更に接続状態を保持できる。
【００１２】また、熱応力によって、有機基板１６が変
形した場合、半導体チップ１３と同指数の弾性率をもつ
堅い接着剤１１と、有機基板１６に塗付された硬化後有
機基板１６と同指数の弾性率をもつ柔らかい接着剤１４
の界面に応力が集中するため、バンプ電極１２と配線１
５の接合部にかかる応力を緩和できる。
【００１３】（実施例３）本発明の実施例を図５、図６
に示す。基板は有機基板２６を用いた場合で、以下に説
明する。
【００１４】まず図５に示すように、半導体チップ２３
のバンプ電極２２を有する面と有機基板２６の配線２５
を有する面に、二液型接着剤をディスペンサ２７により
塗付する。二液型接着剤は、硬化後１０5（ＭＰａ）弾
性率をもつ堅い接着剤２１、と硬化後１０2〜１０4（Ｍ
Ｐａ）の弾性率をもつ柔らかい接着剤２４を用いる。二
液型接着剤を半導体チップ２３面には、硬化後１０
5（ＭＰａ）弾性率をもつ堅い接着剤２１を半導体チッ
プ２３のほぼ中央付近に塗付し、有機基板２６には硬化
後１０2〜１０4（ＭＰａ）の弾性率をもつ柔らかい接着
剤２４を有機基板２６の配線２５周辺に塗付する。
【００１５】次に図６に示すように、半導体チップ２３
を反転させ、半導体チップ２３のバンプ電極２２と有機
基板２６の配線２５を位置合わせした後、半導体チップ
２３と有機基板２６のそれぞれに塗布した二液型接着剤
を張り合わさるように、半導体チップ２３を有機基板２
６上に搭載する。この時、半導体チップ２３に塗付され
た硬化後１０5（ＭＰａ）弾性率をもつ堅い接着剤２１
と、有機基板２６に塗付された硬化後１０2〜１０4（Ｍ
Ｐａ）の弾性率をもつ柔らかい接着剤２４は混合され、
１０分で硬化し、バンプ電極２２と配線２５は電気的に
接続され、更に接続状態を保持できる。
【００１６】また、熱応力によって、有機基板２６が変
形した場合、半導体チップ２３の中心付近では硬化後１
０5（ＭＰａ）弾性率をもつ堅い接着剤２１を用いてい
るため、有機基板２６の変形を抑えることができ、バン
プ電極部２２と配線２５部分の接続部では硬化後１０2
〜１０4（ＭＰａ）の弾性率をもつ柔らかい接着剤２４
を用いているため、バンプ電極２２と配線２５の接続部
にかかる応力集中を緩和できる。
【００１７】
【発明の効果】本発明によれば、二液型接着剤を用いる
ことにより、加圧ツール、及び加圧治具といったもので
加圧する必要がないため、組立工程は簡単であり、組立
コストを低減でき、更に高信頼性を得ることができる。
【図面の簡単な説明】
【図１】本発明の実施例１のプロセスの説明図。
【図２】図１のＡ−Ａ'の断面から見た実施例１のプロ
セスの説明図。
【図３】本発明の実施例２プロセス図。
【図４】図３のＢ−Ｂ'の断面から見た実施例２のプロ
セスの説明図。
【図５】本発明の実施例３のプロセスの説明図。
【図６】図５のＣ−Ｃ'の断面から見た実施例３のプロ
セスの説明図。
【符号の説明】
１…二液型接着剤、 ２…バンプ電極、 ３…半導体チップ、 ４…配線、 ５…基板、 ６…ディスペンサ。
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大関 良雄 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 田島 哲夫 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内

Claims (4)

    【特許請求の範囲】
  1. 【請求項１】基板に半導体チップをフェースダウンで直
    接搭載するフリップチップ接続方法において、二液型接
    着剤を上記半導体チップのバンプ電極を有する面と上記
    基板の配線を有する面に塗布し、上記半導体チップの上
    記バンプ電極と基板配線を位置合わせした後、上記半導
    体チップを上記基板上に搭載すると、二液型接着剤は短
    時間で硬化し、上記半導体チップのバンプ電極と基板の
    配線を電気的に接続することを特徴とするフリップチッ
    プ接続方法。
  2. 【請求項２】請求項１において、上記半導体チップの上
    記バンプ電極を有する面には、アクリル系の接着剤を、
    上記基板の配線を有する面には、シリコン系の接着剤
    を、塗布するフリップチップ接続方法。
  3. 【請求項３】請求項１において、上記半導体チップの上
    記バンプ電極を有する面には、上記半導体チップと同指
    数の弾性率をもつ堅い接着剤を、上記基板の配線を有す
    る面には、上記基板と同指数の弾性率をもつ柔らかい接
    着剤を、塗布するフリップチップ接続方法。
  4. 【請求項４】請求項１において、上記半導体チップの上
    記バンプ電極を有する面には、１０5（ＭＰａ）弾性率
    をもつ堅い接着剤を、上記基板の配線を有する面には、
    １０2〜１０4（ＭＰａ）の弾性率をもつ柔らかい接着剤
    を、塗布するフリップチップ接続方法。
JP8174582A 1996-07-04 1996-07-04 フリップチップ接続方法 Pending JPH1022338A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8174582A JPH1022338A (ja) 1996-07-04 1996-07-04 フリップチップ接続方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8174582A JPH1022338A (ja) 1996-07-04 1996-07-04 フリップチップ接続方法

Publications (1)

Publication Number Publication Date
JPH1022338A true JPH1022338A (ja) 1998-01-23

Family

ID=15981084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8174582A Pending JPH1022338A (ja) 1996-07-04 1996-07-04 フリップチップ接続方法

Country Status (1)

Country Link
JP (1) JPH1022338A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002065541A3 (de) * 2001-02-13 2003-03-20 Pac Tech Gmbh Presskontaktierung von mikrochips
WO2003028094A3 (en) * 2001-09-28 2003-11-06 Hrl Lab Llc Method of self-assembly of electronic or optical components using an adhesive
US7018575B2 (en) 2001-09-28 2006-03-28 Hrl Laboratories, Llc Method for assembly of complementary-shaped receptacle site and device microstructures
US7223635B1 (en) 2003-07-25 2007-05-29 Hrl Laboratories, Llc Oriented self-location of microstructures with alignment structures
US7253091B2 (en) 2001-09-28 2007-08-07 Hrl Laboratories, Llc Process for assembling three-dimensional systems on a chip and structure thus obtained
US7351660B2 (en) 2001-09-28 2008-04-01 Hrl Laboratories, Llc Process for producing high performance interconnects
US11562984B1 (en) 2020-10-14 2023-01-24 Hrl Laboratories, Llc Integrated mechanical aids for high accuracy alignable-electrical contacts

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002065541A3 (de) * 2001-02-13 2003-03-20 Pac Tech Gmbh Presskontaktierung von mikrochips
WO2003028094A3 (en) * 2001-09-28 2003-11-06 Hrl Lab Llc Method of self-assembly of electronic or optical components using an adhesive
US6974604B2 (en) 2001-09-28 2005-12-13 Hrl Laboratories, Llc Method of self-latching for adhesion during self-assembly of electronic or optical components
US7018575B2 (en) 2001-09-28 2006-03-28 Hrl Laboratories, Llc Method for assembly of complementary-shaped receptacle site and device microstructures
US7253091B2 (en) 2001-09-28 2007-08-07 Hrl Laboratories, Llc Process for assembling three-dimensional systems on a chip and structure thus obtained
US7351660B2 (en) 2001-09-28 2008-04-01 Hrl Laboratories, Llc Process for producing high performance interconnects
US7223635B1 (en) 2003-07-25 2007-05-29 Hrl Laboratories, Llc Oriented self-location of microstructures with alignment structures
US7622813B2 (en) 2003-07-25 2009-11-24 Hrl Laboratories, Llc Oriented self-location of microstructures with alignment structures
US11562984B1 (en) 2020-10-14 2023-01-24 Hrl Laboratories, Llc Integrated mechanical aids for high accuracy alignable-electrical contacts

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