JPH10150105A5 - - Google Patents
Info
- Publication number
- JPH10150105A5 JPH10150105A5 JP1997114656A JP11465697A JPH10150105A5 JP H10150105 A5 JPH10150105 A5 JP H10150105A5 JP 1997114656 A JP1997114656 A JP 1997114656A JP 11465697 A JP11465697 A JP 11465697A JP H10150105 A5 JPH10150105 A5 JP H10150105A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor device
- dielectric constant
- organic low
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11465697A JP3997494B2 (ja) | 1996-09-17 | 1997-05-02 | 半導体装置 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8-244375 | 1996-09-17 | ||
| JP24437596 | 1996-09-17 | ||
| JP11465697A JP3997494B2 (ja) | 1996-09-17 | 1997-05-02 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH10150105A JPH10150105A (ja) | 1998-06-02 |
| JPH10150105A5 true JPH10150105A5 (enExample) | 2005-11-04 |
| JP3997494B2 JP3997494B2 (ja) | 2007-10-24 |
Family
ID=26453364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11465697A Expired - Fee Related JP3997494B2 (ja) | 1996-09-17 | 1997-05-02 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3997494B2 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3177968B2 (ja) * | 1998-12-04 | 2001-06-18 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| US6265780B1 (en) * | 1998-12-01 | 2001-07-24 | United Microelectronics Corp. | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
| TW437040B (en) * | 1998-08-12 | 2001-05-28 | Applied Materials Inc | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
| US6297163B1 (en) * | 1998-09-30 | 2001-10-02 | Lam Research Corporation | Method of plasma etching dielectric materials |
| JP2000133710A (ja) | 1998-10-26 | 2000-05-12 | Tokyo Electron Ltd | 半導体装置及びその製造方法 |
| JP2000174123A (ja) | 1998-12-09 | 2000-06-23 | Nec Corp | 半導体装置及びその製造方法 |
| JP3353743B2 (ja) | 1999-05-18 | 2002-12-03 | 日本電気株式会社 | 半導体装置とその製造方法 |
| JP4173307B2 (ja) * | 1999-06-24 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体集積回路の製造方法 |
| US6596623B1 (en) * | 2000-03-17 | 2003-07-22 | Advanced Micro Devices, Inc. | Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers |
| JP3403373B2 (ja) | 2000-05-26 | 2003-05-06 | 松下電器産業株式会社 | 有機膜のエッチング方法、半導体装置の製造方法及びパターンの形成方法 |
| JP3403374B2 (ja) | 2000-05-26 | 2003-05-06 | 松下電器産業株式会社 | 有機膜のエッチング方法、半導体装置の製造方法及びパターンの形成方法 |
| JP3946471B2 (ja) | 2001-07-24 | 2007-07-18 | シャープ株式会社 | 半導体装置の製造方法 |
| JP2003142579A (ja) | 2001-11-07 | 2003-05-16 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
| JP4737361B2 (ja) * | 2003-12-19 | 2011-07-27 | Jsr株式会社 | 絶縁膜およびその形成方法 |
| US6974772B1 (en) * | 2004-08-19 | 2005-12-13 | Intel Corporation | Integrated low-k hard mask |
| JP4762280B2 (ja) * | 2008-08-06 | 2011-08-31 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN115942749A (zh) | 2016-09-21 | 2023-04-07 | 铠侠股份有限公司 | 半导体装置 |
-
1997
- 1997-05-02 JP JP11465697A patent/JP3997494B2/ja not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH10150105A5 (enExample) | ||
| US7285474B2 (en) | Air-gap insulated interconnections | |
| EP0667036B1 (en) | Chip interconnection having a breathable etch stop layer | |
| US7888800B2 (en) | Dummy metal fill shapes for improved reliability of hybrid oxide/low-k dielectrics | |
| KR100634904B1 (ko) | 전자 디바이스 제조 방법 | |
| JP2006506806A5 (enExample) | ||
| US6707156B2 (en) | Semiconductor device with multilevel wiring layers | |
| TW201007883A (en) | Method of sealing an air gap in a layer of a semiconductor structure and semiconductor structure | |
| JP2001326222A (ja) | 半導体装置、半導体ウェーハおよびこれらの製造方法 | |
| JP2971454B2 (ja) | 半導体装置とその製造方法 | |
| US6239019B1 (en) | Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics | |
| KR100382376B1 (ko) | 반도체 장치 및 그의 제조방법 | |
| JP2001284454A (ja) | マルチレベル共面相互接続構造 | |
| CN101587858B (zh) | 半导体器件互连结构及其制作方法 | |
| JP2003303880A5 (enExample) | ||
| KR100571391B1 (ko) | 반도체 소자의 금속 배선 구조의 제조 방법 | |
| TW444346B (en) | Semiconductor device and manufacture thereof | |
| EP2283517B1 (en) | Integrated circuit manufacturing method and integrated circuit | |
| JP2922146B2 (ja) | 半導体素子の絶縁膜平坦化方法 | |
| JP4263053B2 (ja) | 半導体装置の製造方法 | |
| JP2006114723A (ja) | 半導体装置及びその製造方法 | |
| CN103681463A (zh) | 一种双大马士革结构的制备方法 | |
| KR970063677A (ko) | 멀티레벨 상호 접속 반도체 장치와 제조 방법 | |
| KR970003530A (ko) | 미세 반도체 소자의 콘택홀 형성방법 | |
| US7387960B2 (en) | Dual depth trench termination method for improving Cu-based interconnect integrity |