JPH09129670A - フリップチップのための接点高密度型ボール・グリッド・アレー・パッケージ - Google Patents
フリップチップのための接点高密度型ボール・グリッド・アレー・パッケージInfo
- Publication number
- JPH09129670A JPH09129670A JP8264094A JP26409496A JPH09129670A JP H09129670 A JPH09129670 A JP H09129670A JP 8264094 A JP8264094 A JP 8264094A JP 26409496 A JP26409496 A JP 26409496A JP H09129670 A JPH09129670 A JP H09129670A
- Authority
- JP
- Japan
- Prior art keywords
- package
- substrate
- conductive layer
- conductive
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/15—Containers comprising an insulating or insulated base
- H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/654—Top-view layouts
- H10W70/655—Fan-out layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/856—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/60—Seals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US538631 | 1983-10-03 | ||
| US08/538,631 US5637920A (en) | 1995-10-04 | 1995-10-04 | High contact density ball grid array package for flip-chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09129670A true JPH09129670A (ja) | 1997-05-16 |
| JPH09129670A5 JPH09129670A5 (https=) | 2004-10-14 |
Family
ID=24147740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8264094A Pending JPH09129670A (ja) | 1995-10-04 | 1996-10-04 | フリップチップのための接点高密度型ボール・グリッド・アレー・パッケージ |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US5637920A (https=) |
| JP (1) | JPH09129670A (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218882A (ja) * | 2007-03-07 | 2008-09-18 | Nec Electronics Corp | 半導体装置 |
Families Citing this family (195)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773195A (en) * | 1994-12-01 | 1998-06-30 | International Business Machines Corporation | Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic structures including the cap, and a process of forming the cap and for forming multi-layer electronic structures including the cap |
| US5661082A (en) * | 1995-01-20 | 1997-08-26 | Motorola, Inc. | Process for forming a semiconductor device having a bond pad |
| JP3116130B2 (ja) * | 1995-12-19 | 2000-12-11 | 住友金属工業株式会社 | Bga接続構造の形成方法 |
| US5796589A (en) * | 1995-12-20 | 1998-08-18 | Intel Corporation | Ball grid array integrated circuit package that has vias located within the solder pads of a package |
| KR0179802B1 (ko) * | 1995-12-29 | 1999-03-20 | 문정환 | 반도체 패키지 |
| US5764485A (en) * | 1996-04-19 | 1998-06-09 | Lebaschi; Ali | Multi-layer PCB blockade-via pad-connection |
| US6351389B1 (en) * | 1996-05-07 | 2002-02-26 | Sun Microsystems, Inc. | Device and method for packaging an electronic device |
| JP2770820B2 (ja) * | 1996-07-01 | 1998-07-02 | 日本電気株式会社 | 半導体装置の実装構造 |
| US5731073A (en) * | 1996-10-01 | 1998-03-24 | W. L. Gore & Associates, Inc. | Reusable, selectively conductive, Z-axis, elastomeric composite substrate |
| US20040124545A1 (en) * | 1996-12-09 | 2004-07-01 | Daniel Wang | High density integrated circuits and the method of packaging the same |
| US6635514B1 (en) * | 1996-12-12 | 2003-10-21 | Tessera, Inc. | Compliant package with conductive elastomeric posts |
| US6098283A (en) * | 1996-12-19 | 2000-08-08 | Intel Corporation | Method for filling vias in organic, multi-layer packages |
| US5866442A (en) | 1997-01-28 | 1999-02-02 | Micron Technology, Inc. | Method and apparatus for filling a gap between spaced layers of a semiconductor |
| WO1998048449A2 (en) * | 1997-04-21 | 1998-10-29 | Flip Chip Technologies, L.L.C. | Flip chip and chip scale package |
| US6114763A (en) * | 1997-05-30 | 2000-09-05 | Tessera, Inc. | Semiconductor package with translator for connection to an external substrate |
| US6730541B2 (en) * | 1997-11-20 | 2004-05-04 | Texas Instruments Incorporated | Wafer-scale assembly of chip-size packages |
| WO1999034654A1 (en) * | 1997-12-29 | 1999-07-08 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| US6201301B1 (en) | 1998-01-21 | 2001-03-13 | Lsi Logic Corporation | Low cost thermally enhanced flip chip BGA |
| US6329712B1 (en) | 1998-03-25 | 2001-12-11 | Micron Technology, Inc. | High density flip chip memory arrays |
| US6501157B1 (en) | 1998-04-15 | 2002-12-31 | Micron Technology, Inc. | Substrate for accepting wire bonded or flip-chip components |
| US6406939B1 (en) | 1998-05-02 | 2002-06-18 | Charles W. C. Lin | Flip chip assembly with via interconnection |
| SG75841A1 (en) | 1998-05-02 | 2000-10-24 | Eriston Invest Pte Ltd | Flip chip assembly with via interconnection |
| US6266249B1 (en) | 1998-10-20 | 2001-07-24 | Lsi Logic Corporation | Semiconductor flip chip ball grid array package |
| TW396462B (en) | 1998-12-17 | 2000-07-01 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with solder via |
| TW522536B (en) | 1998-12-17 | 2003-03-01 | Wen-Chiang Lin | Bumpless flip chip assembly with strips-in-via and plating |
| TW444236B (en) | 1998-12-17 | 2001-07-01 | Charles Wen Chyang Lin | Bumpless flip chip assembly with strips and via-fill |
| US6023097A (en) * | 1999-03-17 | 2000-02-08 | Chipmos Technologies, Inc. | Stacked multiple-chip module micro ball grid array packaging |
| US6288905B1 (en) * | 1999-04-15 | 2001-09-11 | Amerasia International Technology Inc. | Contact module, as for a smart card, and method for making same |
| GB2356287B (en) * | 1999-07-15 | 2004-03-24 | Altera Corp | Apparatus and method for packaging different sized semiconductor chips on a common substrate |
| US6351144B1 (en) * | 1999-07-15 | 2002-02-26 | Altera Corporation | Programmable logic device with unified cell structure including signal interface bumps |
| US6407450B1 (en) | 1999-07-15 | 2002-06-18 | Altera Corporation | Semiconductor package with universal substrate for electrically interfacing with different sized chips that have different logic functions |
| US6392428B1 (en) * | 1999-11-16 | 2002-05-21 | Eaglestone Partners I, Llc | Wafer level interposer |
| US6154366A (en) * | 1999-11-23 | 2000-11-28 | Intel Corporation | Structures and processes for fabricating moisture resistant chip-on-flex packages |
| SE516936C2 (sv) * | 1999-12-10 | 2002-03-26 | Ericsson Telefon Ab L M | Flytande-kristalldisplay, LCD |
| TW434664B (en) * | 1999-12-29 | 2001-05-16 | Advanced Semiconductor Eng | Lead-bond type chip package and method for making the same |
| US6376265B1 (en) * | 2000-04-05 | 2002-04-23 | Advanced Micro Devices, Inc. | Non-contact automatic height sensing using air pressure for die bonding |
| JP2001326304A (ja) * | 2000-05-15 | 2001-11-22 | Toshiba Corp | 半導体装置及びその製造方法 |
| US6507118B1 (en) | 2000-07-14 | 2003-01-14 | 3M Innovative Properties Company | Multi-metal layer circuit |
| US6898773B1 (en) | 2002-01-22 | 2005-05-24 | Cadence Design Systems, Inc. | Method and apparatus for producing multi-layer topological routes |
| US6889372B1 (en) | 2000-07-15 | 2005-05-03 | Cadence Design Systems Inc. | Method and apparatus for routing |
| US6812048B1 (en) * | 2000-07-31 | 2004-11-02 | Eaglestone Partners I, Llc | Method for manufacturing a wafer-interposer assembly |
| US6537831B1 (en) * | 2000-07-31 | 2003-03-25 | Eaglestone Partners I, Llc | Method for selecting components for a matched set using a multi wafer interposer |
| US6822469B1 (en) * | 2000-07-31 | 2004-11-23 | Eaglestone Partners I, Llc | Method for testing multiple semiconductor wafers |
| US6660626B1 (en) | 2000-08-22 | 2003-12-09 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
| US6551861B1 (en) | 2000-08-22 | 2003-04-22 | Charles W. C. Lin | Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive |
| US6562709B1 (en) | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
| US6436734B1 (en) | 2000-08-22 | 2002-08-20 | Charles W. C. Lin | Method of making a support circuit for a semiconductor chip assembly |
| US6350633B1 (en) | 2000-08-22 | 2002-02-26 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
| US6562657B1 (en) | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
| US6402970B1 (en) | 2000-08-22 | 2002-06-11 | Charles W. C. Lin | Method of making a support circuit for a semiconductor chip assembly |
| US6403460B1 (en) | 2000-08-22 | 2002-06-11 | Charles W. C. Lin | Method of making a semiconductor chip assembly |
| JP3722209B2 (ja) * | 2000-09-05 | 2005-11-30 | セイコーエプソン株式会社 | 半導体装置 |
| US6350632B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Semiconductor chip assembly with ball bond connection joint |
| US6511865B1 (en) | 2000-09-20 | 2003-01-28 | Charles W. C. Lin | Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly |
| US6350386B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly |
| US6417463B1 (en) * | 2000-10-02 | 2002-07-09 | Apple Computer, Inc. | Depopulation of a ball grid array to allow via placement |
| US6544813B1 (en) | 2000-10-02 | 2003-04-08 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
| US6448108B1 (en) | 2000-10-02 | 2002-09-10 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
| US6815712B1 (en) | 2000-10-02 | 2004-11-09 | Eaglestone Partners I, Llc | Method for selecting components for a matched set from a wafer-interposer assembly |
| US7264991B1 (en) | 2000-10-13 | 2007-09-04 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using conductive adhesive |
| US7190080B1 (en) | 2000-10-13 | 2007-03-13 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
| US7129575B1 (en) | 2000-10-13 | 2006-10-31 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped metal pillar |
| US7414319B2 (en) * | 2000-10-13 | 2008-08-19 | Bridge Semiconductor Corporation | Semiconductor chip assembly with metal containment wall and solder terminal |
| US6537851B1 (en) | 2000-10-13 | 2003-03-25 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace to a semiconductor chip |
| US6876072B1 (en) | 2000-10-13 | 2005-04-05 | Bridge Semiconductor Corporation | Semiconductor chip assembly with chip in substrate cavity |
| US6576493B1 (en) | 2000-10-13 | 2003-06-10 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
| US6949408B1 (en) | 2000-10-13 | 2005-09-27 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
| US6740576B1 (en) | 2000-10-13 | 2004-05-25 | Bridge Semiconductor Corporation | Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly |
| US6492252B1 (en) | 2000-10-13 | 2002-12-10 | Bridge Semiconductor Corporation | Method of connecting a bumped conductive trace to a semiconductor chip |
| US6667229B1 (en) | 2000-10-13 | 2003-12-23 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip |
| US7262082B1 (en) | 2000-10-13 | 2007-08-28 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture |
| US7094676B1 (en) | 2000-10-13 | 2006-08-22 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
| US6699780B1 (en) | 2000-10-13 | 2004-03-02 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching |
| US7009297B1 (en) | 2000-10-13 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal particle |
| US6984576B1 (en) | 2000-10-13 | 2006-01-10 | Bridge Semiconductor Corporation | Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip |
| US7075186B1 (en) | 2000-10-13 | 2006-07-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with interlocked contact terminal |
| US6548393B1 (en) | 2000-10-13 | 2003-04-15 | Charles W. C. Lin | Semiconductor chip assembly with hardened connection joint |
| US6908788B1 (en) | 2000-10-13 | 2005-06-21 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using a metal base |
| US6872591B1 (en) | 2000-10-13 | 2005-03-29 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a conductive trace and a substrate |
| US7132741B1 (en) | 2000-10-13 | 2006-11-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with carved bumped terminal |
| US7319265B1 (en) | 2000-10-13 | 2008-01-15 | Bridge Semiconductor Corporation | Semiconductor chip assembly with precision-formed metal pillar |
| US7071089B1 (en) | 2000-10-13 | 2006-07-04 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a carved bumped terminal |
| US6440835B1 (en) | 2000-10-13 | 2002-08-27 | Charles W. C. Lin | Method of connecting a conductive trace to a semiconductor chip |
| US6673710B1 (en) | 2000-10-13 | 2004-01-06 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip |
| US7129113B1 (en) | 2000-10-13 | 2006-10-31 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture |
| US6576539B1 (en) | 2000-10-13 | 2003-06-10 | Charles W.C. Lin | Semiconductor chip assembly with interlocked conductive trace |
| US7345316B2 (en) * | 2000-10-25 | 2008-03-18 | Shipley Company, L.L.C. | Wafer level packaging for optoelectronic devices |
| US6686657B1 (en) * | 2000-11-07 | 2004-02-03 | Eaglestone Partners I, Llc | Interposer for improved handling of semiconductor wafers and method of use of same |
| US6932519B2 (en) | 2000-11-16 | 2005-08-23 | Shipley Company, L.L.C. | Optical device package |
| US7080336B2 (en) * | 2000-12-06 | 2006-07-18 | Cadence Design Systems, Inc. | Method and apparatus for computing placement costs |
| US7024650B2 (en) * | 2000-12-06 | 2006-04-04 | Cadence Design Systems, Inc. | Method and apparatus for considering diagonal wiring in placement |
| AU2002233977A1 (en) * | 2000-12-06 | 2002-06-18 | Simplex Solutions, Inc. | Method and apparatus for considering diagonal wiring in placement |
| US7003754B2 (en) * | 2000-12-07 | 2006-02-21 | Cadence Design Systems, Inc. | Routing method and apparatus that use of diagonal routes |
| US6516455B1 (en) * | 2000-12-06 | 2003-02-04 | Cadence Design Systems, Inc. | Partitioning placement method using diagonal cutlines |
| US7055120B2 (en) * | 2000-12-06 | 2006-05-30 | Cadence Design Systems, Inc. | Method and apparatus for placing circuit modules |
| US6826737B2 (en) * | 2000-12-06 | 2004-11-30 | Cadence Design Systems, Inc. | Recursive partitioning placement method and apparatus |
| US6957410B2 (en) * | 2000-12-07 | 2005-10-18 | Cadence Design Systems, Inc. | Method and apparatus for adaptively selecting the wiring model for a design region |
| US7073150B2 (en) * | 2000-12-07 | 2006-07-04 | Cadence Design Systems, Inc. | Hierarchical routing method and apparatus that use diagonal routes |
| US6900540B1 (en) * | 2000-12-07 | 2005-05-31 | Cadence Design Systems, Inc. | Simulating diagonal wiring directions using Manhattan directional wires |
| US6858928B1 (en) * | 2000-12-07 | 2005-02-22 | Cadence Design Systems, Inc. | Multi-directional wiring on a single metal layer |
| US6883977B2 (en) | 2000-12-14 | 2005-04-26 | Shipley Company, L.L.C. | Optical device package for flip-chip mounting |
| US20020076854A1 (en) * | 2000-12-15 | 2002-06-20 | Pierce John L. | System, method and apparatus for constructing a semiconductor wafer-interposer using B-Stage laminates |
| US20020078401A1 (en) * | 2000-12-15 | 2002-06-20 | Fry Michael Andrew | Test coverage analysis system |
| US6444489B1 (en) | 2000-12-15 | 2002-09-03 | Charles W. C. Lin | Semiconductor chip assembly with bumped molded substrate |
| US6529022B2 (en) * | 2000-12-15 | 2003-03-04 | Eaglestone Pareners I, Llc | Wafer testing interposer for a conventional package |
| US6524885B2 (en) * | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
| US6738960B2 (en) * | 2001-01-19 | 2004-05-18 | Cadence Design Systems, Inc. | Method and apparatus for producing sub-optimal routes for a net by generating fake configurations |
| US6915501B2 (en) | 2001-01-19 | 2005-07-05 | Cadence Design Systems, Inc. | LP method and apparatus for identifying routes |
| US6653170B1 (en) | 2001-02-06 | 2003-11-25 | Charles W. C. Lin | Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit |
| US6673653B2 (en) * | 2001-02-23 | 2004-01-06 | Eaglestone Partners I, Llc | Wafer-interposer using a ceramic substrate |
| US6571468B1 (en) * | 2001-02-26 | 2003-06-03 | Saturn Electronics & Engineering, Inc. | Traceless flip chip assembly and method |
| US6713318B2 (en) | 2001-03-28 | 2004-03-30 | Intel Corporation | Flip chip interconnection using no-clean flux |
| US6495397B2 (en) | 2001-03-28 | 2002-12-17 | Intel Corporation | Fluxless flip chip interconnection |
| JP4129717B2 (ja) * | 2001-05-30 | 2008-08-06 | 株式会社ルネサステクノロジ | 半導体装置 |
| US7069530B1 (en) | 2001-06-03 | 2006-06-27 | Cadence Design Systems, Inc. | Method and apparatus for routing groups of paths |
| US7107564B1 (en) | 2001-06-03 | 2006-09-12 | Cadence Design Systems, Inc. | Method and apparatus for routing a set of nets |
| US6895567B1 (en) | 2001-06-03 | 2005-05-17 | Cadence Design Systems, Inc. | Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs |
| US6957408B1 (en) | 2002-01-22 | 2005-10-18 | Cadence Design Systems, Inc. | Method and apparatus for routing nets in an integrated circuit layout |
| US6951005B1 (en) | 2001-06-03 | 2005-09-27 | Cadence Design Systems, Inc. | Method and apparatus for selecting a route for a net based on the impact on other nets |
| US6829757B1 (en) | 2001-06-03 | 2004-12-07 | Cadence Design Systems, Inc. | Method and apparatus for generating multi-layer routes |
| US6877146B1 (en) | 2001-06-03 | 2005-04-05 | Cadence Design Systems, Inc. | Method and apparatus for routing a set of nets |
| US6957411B1 (en) | 2001-06-03 | 2005-10-18 | Cadence Design Systems, Inc. | Gridless IC layout and method and apparatus for generating such a layout |
| US7061102B2 (en) | 2001-06-11 | 2006-06-13 | Xilinx, Inc. | High performance flipchip package that incorporates heat removal with minimal thermal mismatch |
| US7155697B2 (en) * | 2001-08-23 | 2006-12-26 | Cadence Design Systems, Inc. | Routing method and apparatus |
| US6931616B2 (en) * | 2001-08-23 | 2005-08-16 | Cadence Design Systems, Inc. | Routing method and apparatus |
| US7143382B2 (en) | 2001-08-23 | 2006-11-28 | Cadence Design Systems, Inc. | Method and apparatus for storing routes |
| US6795958B2 (en) | 2001-08-23 | 2004-09-21 | Cadence Design Systems, Inc. | Method and apparatus for generating routes for groups of related node configurations |
| DE10141753A1 (de) * | 2001-08-29 | 2003-03-20 | Orga Kartensysteme Gmbh | Verfahren zur Montage eines elektronischen Bauelementes auf einer Trägerstuktur in Face-Down-Technik |
| US7058913B1 (en) * | 2001-09-06 | 2006-06-06 | Cadence Design Systems, Inc. | Analytical placement method and apparatus |
| US6576992B1 (en) * | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
| TWI286826B (en) * | 2001-12-28 | 2007-09-11 | Via Tech Inc | Semiconductor package substrate and process thereof |
| US6938234B1 (en) | 2002-01-22 | 2005-08-30 | Cadence Design Systems, Inc. | Method and apparatus for defining vias |
| US6892371B1 (en) | 2002-01-22 | 2005-05-10 | Cadence Design Systems, Inc. | Method and apparatus for performing geometric routing |
| US7096449B1 (en) | 2002-01-22 | 2006-08-22 | Cadence Design Systems, Inc. | Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts |
| US7080329B1 (en) | 2002-01-22 | 2006-07-18 | Cadence Design Systems, Inc. | Method and apparatus for identifying optimized via locations |
| US6944841B1 (en) | 2002-01-22 | 2005-09-13 | Cadence Design Systems, Inc. | Method and apparatus for proportionate costing of vias |
| US7013451B1 (en) | 2002-01-22 | 2006-03-14 | Cadence Design Systems, Inc. | Method and apparatus for performing routability checking |
| US7036105B1 (en) | 2002-01-22 | 2006-04-25 | Cadence Design Systems, Inc. | Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's |
| US7089524B1 (en) | 2002-01-22 | 2006-08-08 | Cadence Design Systems, Inc. | Topological vias route wherein the topological via does not have a coordinate within the region |
| US7117468B1 (en) | 2002-01-22 | 2006-10-03 | Cadence Design Systems, Inc. | Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts |
| US6930381B1 (en) * | 2002-04-12 | 2005-08-16 | Apple Computer, Inc. | Wire bonding method and apparatus for integrated circuit |
| US6680530B1 (en) | 2002-08-12 | 2004-01-20 | International Business Machines Corporation | Multi-step transmission line for multilayer packaging |
| US6996789B2 (en) * | 2002-11-18 | 2006-02-07 | Cadence Design Systems, Inc. | Method and apparatus for performing an exponential path search |
| US7047513B2 (en) * | 2002-11-18 | 2006-05-16 | Cadence Design Systems, Inc. | Method and apparatus for searching for a three-dimensional global path |
| US7080342B2 (en) * | 2002-11-18 | 2006-07-18 | Cadence Design Systems, Inc | Method and apparatus for computing capacity of a region for non-Manhattan routing |
| US6892369B2 (en) * | 2002-11-18 | 2005-05-10 | Cadence Design Systems, Inc. | Method and apparatus for costing routes of nets |
| US7093221B2 (en) * | 2002-11-18 | 2006-08-15 | Cadence Design Systems, Inc. | Method and apparatus for identifying a group of routes for a set of nets |
| US7171635B2 (en) * | 2002-11-18 | 2007-01-30 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US7480885B2 (en) * | 2002-11-18 | 2009-01-20 | Cadence Design Systems, Inc. | Method and apparatus for routing with independent goals on different layers |
| US7216308B2 (en) * | 2002-11-18 | 2007-05-08 | Cadence Design Systems, Inc. | Method and apparatus for solving an optimization problem in an integrated circuit layout |
| US7624367B2 (en) | 2002-11-18 | 2009-11-24 | Cadence Design Systems, Inc. | Method and system for routing |
| US7003752B2 (en) * | 2002-11-18 | 2006-02-21 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US6988257B2 (en) * | 2002-11-18 | 2006-01-17 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US7010771B2 (en) * | 2002-11-18 | 2006-03-07 | Cadence Design Systems, Inc. | Method and apparatus for searching for a global path |
| US7013445B1 (en) | 2002-12-31 | 2006-03-14 | Cadence Design Systems, Inc. | Post processor for optimizing manhattan integrated circuits placements into non manhattan placements |
| US7506295B1 (en) | 2002-12-31 | 2009-03-17 | Cadence Design Systems, Inc. | Non manhattan floor plan architecture for integrated circuits |
| US7089519B1 (en) | 2002-12-31 | 2006-08-08 | Cadence Design System, Inc. | Method and system for performing placement on non Manhattan semiconductor integrated circuits |
| TWI278975B (en) * | 2003-03-04 | 2007-04-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with heatsink |
| TWI265611B (en) * | 2003-03-11 | 2006-11-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with heatsink |
| AU2003901146A0 (en) * | 2003-03-12 | 2003-03-27 | Cochlear Limited | Feedthrough assembly |
| TWI273680B (en) * | 2003-03-27 | 2007-02-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with embedded heat spreader abstract of the disclosure |
| TW200428623A (en) * | 2003-06-11 | 2004-12-16 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat sink |
| JP4046026B2 (ja) * | 2003-06-27 | 2008-02-13 | 株式会社日立製作所 | 半導体装置 |
| TWI224846B (en) * | 2003-08-12 | 2004-12-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipating structure |
| TWI242862B (en) | 2003-08-21 | 2005-11-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat sink |
| US7993983B1 (en) | 2003-11-17 | 2011-08-09 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with chip and encapsulant grinding |
| US7538415B1 (en) | 2003-11-20 | 2009-05-26 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal, filler and insulative base |
| US7425759B1 (en) | 2003-11-20 | 2008-09-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal and filler |
| US7373628B1 (en) | 2004-06-01 | 2008-05-13 | Pulsic Limited | Method of automatically routing nets using a Steiner tree |
| US7784010B1 (en) | 2004-06-01 | 2010-08-24 | Pulsic Limited | Automatic routing system with variable width interconnect |
| US7131096B1 (en) | 2004-06-01 | 2006-10-31 | Pulsic Limited | Method of automatically routing nets according to current density rules |
| US8095903B2 (en) | 2004-06-01 | 2012-01-10 | Pulsic Limited | Automatically routing nets with variable spacing |
| US7257797B1 (en) | 2004-06-07 | 2007-08-14 | Pulsic Limited | Method of automatic shape-based routing of interconnects in spines for integrated circuit design |
| US7446419B1 (en) | 2004-11-10 | 2008-11-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar of stacked metal balls |
| US7750483B1 (en) | 2004-11-10 | 2010-07-06 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal |
| US7268421B1 (en) | 2004-11-10 | 2007-09-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond |
| WO2007074402A2 (en) | 2005-06-21 | 2007-07-05 | Pulsic Limited | High-speed shape-based router |
| US7603644B2 (en) * | 2005-06-24 | 2009-10-13 | Pulsic Limited | Integrated circuit routing and compaction |
| JP4797482B2 (ja) * | 2005-07-20 | 2011-10-19 | ブラザー工業株式会社 | 配線基板及び配線基板の製造方法 |
| US7363607B2 (en) | 2005-11-08 | 2008-04-22 | Pulsic Limited | Method of automatically routing nets according to parasitic constraint rules |
| TWI291752B (en) * | 2006-02-27 | 2007-12-21 | Siliconware Precision Industries Co Ltd | Semiconductor package with heat dissipating device and fabrication method thereof |
| TWI306296B (en) * | 2006-04-06 | 2009-02-11 | Siliconware Precision Industries Co Ltd | Semiconductor device with a heat sink and method for fabricating the same |
| US8201128B2 (en) | 2006-06-16 | 2012-06-12 | Cadence Design Systems, Inc. | Method and apparatus for approximating diagonal lines in placement |
| US8250514B1 (en) | 2006-07-13 | 2012-08-21 | Cadence Design Systems, Inc. | Localized routing direction |
| US7494843B1 (en) | 2006-12-26 | 2009-02-24 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding |
| US7811863B1 (en) | 2006-10-26 | 2010-10-12 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment |
| JP2008117997A (ja) * | 2006-11-07 | 2008-05-22 | Seiko Epson Corp | 電子基板の製造方法 |
| US20080162045A1 (en) * | 2006-12-29 | 2008-07-03 | Hung-Fu Lee | Traffic flow and vehicle position detection system |
| US7928574B2 (en) * | 2007-08-22 | 2011-04-19 | Texas Instruments Incorporated | Semiconductor package having buss-less substrate |
| US8458636B1 (en) | 2009-03-18 | 2013-06-04 | Pulsic Limited | Filling vacant areas of an integrated circuit design |
| JP2013197387A (ja) * | 2012-03-21 | 2013-09-30 | Elpida Memory Inc | 半導体装置 |
| US9034694B1 (en) | 2014-02-27 | 2015-05-19 | Freescale Semiconductor, Inc. | Embedded die ball grid array package |
| DE102015116807A1 (de) * | 2015-10-02 | 2017-04-06 | Infineon Technologies Austria Ag | Funktionalisierte Schnittstellenstruktur |
| US11488880B2 (en) * | 2017-06-30 | 2022-11-01 | Intel Corporation | Enclosure for an electronic component |
| CN117038646B (zh) * | 2023-10-08 | 2024-01-26 | 之江实验室 | 陶瓷封装结构及其设计方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3705332A (en) * | 1970-06-25 | 1972-12-05 | Howard L Parks | Electrical circuit packaging structure and method of fabrication thereof |
| US4667401A (en) * | 1985-11-26 | 1987-05-26 | Clements James R | Method of making an electronic device using an uniaxial conductive adhesive |
| JPS63150930A (ja) * | 1986-12-15 | 1988-06-23 | Shin Etsu Polymer Co Ltd | 半導体装置 |
| US4942140A (en) * | 1987-03-25 | 1990-07-17 | Mitsubishi Denki Kabushiki Kaisha | Method of packaging semiconductor device |
| US5157477A (en) * | 1990-01-10 | 1992-10-20 | International Business Machines Corporation | Matched impedance vertical conductors in multilevel dielectric laminated wiring |
| US5121190A (en) * | 1990-03-14 | 1992-06-09 | International Business Machines Corp. | Solder interconnection structure on organic substrates |
| JP2657429B2 (ja) * | 1990-04-09 | 1997-09-24 | 株式会社ミクロ技術研究所 | 基板の回路実装方法及びその方法に使用する回路基板 |
| US5065227A (en) * | 1990-06-04 | 1991-11-12 | International Business Machines Corporation | Integrated circuit packaging using flexible substrate |
| US5203076A (en) * | 1991-12-23 | 1993-04-20 | Motorola, Inc. | Vacuum infiltration of underfill material for flip-chip devices |
| JPH0661383A (ja) * | 1992-08-11 | 1994-03-04 | Fujitsu Ltd | 半導体装置 |
| JPH06244231A (ja) * | 1993-02-01 | 1994-09-02 | Motorola Inc | 気密半導体デバイスおよびその製造方法 |
| US5386624A (en) * | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
| US5434452A (en) * | 1993-11-01 | 1995-07-18 | Motorola, Inc. | Z-axis compliant mechanical IC wiring substrate and method for making the same |
| JPH07169872A (ja) * | 1993-12-13 | 1995-07-04 | Fujitsu Ltd | 半導体装置及びその製造方法 |
-
1995
- 1995-10-04 US US08/538,631 patent/US5637920A/en not_active Expired - Lifetime
-
1996
- 1996-10-04 JP JP8264094A patent/JPH09129670A/ja active Pending
-
1997
- 1997-01-03 US US08/778,909 patent/US5784780A/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008218882A (ja) * | 2007-03-07 | 2008-09-18 | Nec Electronics Corp | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US5784780A (en) | 1998-07-28 |
| US5637920A (en) | 1997-06-10 |
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