JP2008218882A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2008218882A JP2008218882A JP2007057120A JP2007057120A JP2008218882A JP 2008218882 A JP2008218882 A JP 2008218882A JP 2007057120 A JP2007057120 A JP 2007057120A JP 2007057120 A JP2007057120 A JP 2007057120A JP 2008218882 A JP2008218882 A JP 2008218882A
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48091—Arched
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Wire Bonding (AREA)
Abstract
【解決手段】半導体装置は、半導体チップ1端部が、BGA基板9と接合するランド7部の中心(=ハンダボール8の中心)と重ならない。より好ましくは、半導体チップ1の中心とそのチップがマウントされるBGA基板9の中心とが重ならず、かつチップに対して垂直方向において、半導体チップ1端部がBGA基板9のボール中心位置と重ならない。
【選択図】図1
Description
2 パッド
3 ボンディングワイヤ
4、6 BGA基板配線パターン
5 スルーホール
7 ランド
8 半田ボール
9 BGA基板
10 モールド樹脂
11 実装基板
12 金属バンプ
14 スペーサー
15 絶縁テープ
16 接着剤
C1,3 チップ中心位置
C2 BGA基板中心位置
Claims (7)
- 半導体チップと、
前記半導体チップがマウントされる組立基板と、
前記組立基板を実装するためのボールと、
前記組立基板上に前記ボールと前記組立基板とが接続されるランド部と
を備え
前記半導体チップの中心と前記組立基板の中心とをずらすことにより両者の中心を一致させて実装した場合に生じる前記半導体チップの端部と前記ランド部との重なりを防止して両者が重ならないようにしたことを特徴とする半導体装置。 - 前記半導体チップはボンディングにより前記基板と結合されることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップはフリップチップ接続により前記基板と結合されることを特徴とする請求項1に記載の半導体装置。
- 前記ボールは前記基板に等間隔でマトリックス状に配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置はさらに前記半導体チップとは異なる第2の半導体チップを備え、
前記第2の半導体チップのチップエッジも前記ランド部と重ならないこと
を特徴とする請求項1に記載の半導体装置。 - 前記半導体装置はさらに前記チップと前記第2のチップとの間にスペーサを備えることを特徴とする請求項5に記載の半導体装置。
- 半導体チップと、
前記半導体チップがマウントされる組立基板と、
前記組立基板を実装するためのボールと、
前記組立基板上に前記ボールと前記組立基板とが接続されるランド部と
を備え
前記半導体チップの中心と前記組立基板の中心とをずらすことにより前記半導体チップの少なくとも一辺の端部が前記ランド部と重ならないようにしたことを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007057120A JP2008218882A (ja) | 2007-03-07 | 2007-03-07 | 半導体装置 |
US12/071,123 US7683485B2 (en) | 2007-03-07 | 2008-02-15 | Semiconductor device |
CNA2008100834296A CN101261975A (zh) | 2007-03-07 | 2008-03-05 | 半导体器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007057120A JP2008218882A (ja) | 2007-03-07 | 2007-03-07 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008218882A true JP2008218882A (ja) | 2008-09-18 |
Family
ID=39740827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007057120A Pending JP2008218882A (ja) | 2007-03-07 | 2007-03-07 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7683485B2 (ja) |
JP (1) | JP2008218882A (ja) |
CN (1) | CN101261975A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013197501A (ja) * | 2012-03-22 | 2013-09-30 | Hoya Corp | 半導体パッケージ |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5538682B2 (ja) * | 2008-03-06 | 2014-07-02 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
JP2011228603A (ja) | 2010-04-23 | 2011-11-10 | Elpida Memory Inc | 半導体装置の製造方法および半導体装置 |
US8766453B2 (en) * | 2012-10-25 | 2014-07-01 | Freescale Semiconductor, Inc. | Packaged integrated circuit having large solder pads and method for forming |
JP2015220235A (ja) * | 2014-05-14 | 2015-12-07 | マイクロン テクノロジー, インク. | 半導体装置 |
US10784563B2 (en) * | 2018-02-21 | 2020-09-22 | International Business Machines Corporation | Scalable phased array package |
US10826194B2 (en) | 2018-02-21 | 2020-11-03 | International Business Machines Corporation | Scalable phased array package |
CN112582333A (zh) * | 2019-09-27 | 2021-03-30 | 中芯长电半导体(江阴)有限公司 | 一种重新布线层及其制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09129670A (ja) * | 1995-10-04 | 1997-05-16 | Lsi Logic Corp | フリップチップのための接点高密度型ボール・グリッド・アレー・パッケージ |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001144214A (ja) | 1999-11-17 | 2001-05-25 | Canon Inc | 半導体装置およびその接合構造 |
JP4104490B2 (ja) * | 2003-05-21 | 2008-06-18 | オリンパス株式会社 | 半導体装置の製造方法 |
US7126217B2 (en) * | 2004-08-07 | 2006-10-24 | Texas Instruments Incorporated | Arrangement in semiconductor packages for inhibiting adhesion of lid to substrate while providing compression support |
-
2007
- 2007-03-07 JP JP2007057120A patent/JP2008218882A/ja active Pending
-
2008
- 2008-02-15 US US12/071,123 patent/US7683485B2/en active Active
- 2008-03-05 CN CNA2008100834296A patent/CN101261975A/zh active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09129670A (ja) * | 1995-10-04 | 1997-05-16 | Lsi Logic Corp | フリップチップのための接点高密度型ボール・グリッド・アレー・パッケージ |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013197501A (ja) * | 2012-03-22 | 2013-09-30 | Hoya Corp | 半導体パッケージ |
Also Published As
Publication number | Publication date |
---|---|
CN101261975A (zh) | 2008-09-10 |
US20080217774A1 (en) | 2008-09-11 |
US7683485B2 (en) | 2010-03-23 |
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