JPH08507177A - Ｊｆｅｔを備えたｃｍｏｓデバイスの製造プロセス - Google Patents

Ｊｆｅｔを備えたｃｍｏｓデバイスの製造プロセス

Info

Publication number
JPH08507177A
JPH08507177A JP6519263A JP51926394A JPH08507177A JP H08507177 A JPH08507177 A JP H08507177A JP 6519263 A JP6519263 A JP 6519263A JP 51926394 A JP51926394 A JP 51926394A JP H08507177 A JPH08507177 A JP H08507177A
Authority
JP
Japan
Prior art keywords
region
forming
well
mask
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6519263A
Other languages
English (en)
Japanese (ja)
Inventor
メリル，リチャード，ビー
ファーレンコプフ，ダグ，アール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of JPH08507177A publication Critical patent/JPH08507177A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
JP6519263A 1993-02-25 1994-02-18 Ｊｆｅｔを備えたｃｍｏｓデバイスの製造プロセス Pending JPH08507177A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US2379893A 1993-02-25 1993-02-25
US08/023,798 1993-02-25
PCT/US1994/001990 WO1994019828A1 (en) 1993-02-25 1994-02-18 Fabrication process for cmos device with jfet

Publications (1)

Publication Number Publication Date
JPH08507177A true JPH08507177A (ja) 1996-07-30

Family

ID=21817260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6519263A Pending JPH08507177A (ja) 1993-02-25 1994-02-18 Ｊｆｅｔを備えたｃｍｏｓデバイスの製造プロセス

Country Status (5)

Country Link
EP (1) EP0686305A1 (enrdf_load_stackoverflow)
JP (1) JPH08507177A (enrdf_load_stackoverflow)
KR (1) KR960701472A (enrdf_load_stackoverflow)
TW (1) TW232086B (enrdf_load_stackoverflow)
WO (1) WO1994019828A1 (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010177268A (ja) * 2009-01-27 2010-08-12 Asahi Kasei Electronics Co Ltd 接合型ｆｅｔ、半導体装置およびその製造方法
JP2019521527A (ja) * 2016-07-14 2019-07-25 ハイペリオン セミコンダクターズ オサケユイチア 半導体論理素子および論理回路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE230162T1 (de) * 1997-10-02 2003-01-15 Ist Trentino Di Cultura Verfahren zur herstellung eines jfet bauelements
FR2776832B1 (fr) * 1998-03-31 2000-06-16 Sgs Thomson Microelectronics Procede de fabrication de transistors jfet

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53136977A (en) * 1977-05-04 1978-11-29 Seiko Instr & Electronics Ltd Driving circuit
DE2753704C2 (de) * 1977-12-02 1986-11-06 Bernd Prof. Dr. rer.nat 5841 Holzen Höfflinger Verfahren zum gleichzeitigen Herstellen von mittels Feldoxid isolierten CMOS-Schaltungsanordnungen und Bipolartransistoren
US4403395A (en) * 1979-02-15 1983-09-13 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
JPS5854711A (ja) * 1981-09-29 1983-03-31 Nec Corp 差動増幅器
JPS6024056A (ja) * 1984-06-25 1985-02-06 Hitachi Ltd 差動増幅器
JPS6185855A (ja) * 1984-10-04 1986-05-01 Nec Corp 半導体集積回路
US5296409A (en) * 1992-05-08 1994-03-22 National Semiconductor Corporation Method of making n-channel and p-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010177268A (ja) * 2009-01-27 2010-08-12 Asahi Kasei Electronics Co Ltd 接合型ｆｅｔ、半導体装置およびその製造方法
JP2019521527A (ja) * 2016-07-14 2019-07-25 ハイペリオン セミコンダクターズ オサケユイチア 半導体論理素子および論理回路

Also Published As

Publication number Publication date
KR960701472A (ko) 1996-02-24
EP0686305A1 (en) 1995-12-13
TW232086B (enrdf_load_stackoverflow) 1994-10-11
WO1994019828A1 (en) 1994-09-01

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