Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components

Definitions

• the present invention relates generally to the field of semiconductor devices and their fabrication. More specifically, the present invention relates to fabricating a device in a baseline complementary metal-oxide semiconductor (CMOS) technology using only one extra mask and having very low offset drift.
• CMOS complementary metal-oxide semiconductor
• CMOS devices and their fabrication techniques have been well known for many years.
• CMOS devices have a number of very desirable properties, including extremely low power dissipation, that make their use very attractive for digital circuitry, and thus, they are widely used in integrated circuits.
• CMOS devices suffer from high offset drift because current flows at and very near the surface in all CMOS devices.
• imperfections in the lattice structure of the silicon substrate near the surface can adversely affect the current flow.
• Such imperfections are referred to as interface or surface states and occur on integrated circuits where the silicon dioxide layer and silicon substrate meet.
• Interface states are a direct result of silicon and silicon dioxide having different lattice structures.
• the different lattice structures of the two materials prevents a perfect bond from forming between the silicon and silicon dioxide layers and results in the formation of interface states.
• the interface states cause a net charge to form at the interface interfering with current flow and making the threshold voltage difficult to predict.
• Offset drift is not a severe problem in pure digital technology because circuits simply need to distinguish between high and low voltage levels.
• offset drift is problem of great significance in many analog applications such as differential amplifiers and analog-to-digital converters.
• CMOS complementary metal-oxide-semiconductor
• JFETs junction field effect transistors
• a second problem is that surface states in CMOS devices are unpredictable and difficult to control. Many of the reasons surface states are formed are poorly understood. Often, small, seemingly inconsequential changes during the manufacturing stage can result in changed surface state creation. While the surface states may be easy to control during the pilot stages of production, surface states can become a major problem once actual manufacturing starts.
• the present invention seeks to overcome the above problems by creating a device implemented in baseline CMOS technology that has extremely good offset drift and is highly manufacturable.
• the present invention solves the above problem by creating a CMOS process that includes JFET transistors for reducing drift and that uses only one mask that is not standard to the baseline CMOS process.
• the fabrication of the CMOS device of the present invention includes the formation of N-wells, P-wells, field oxide regions, poly interconnections, and N + and P + drain regions on a semiconductor substrate using standard masks of the baseline CMOS process.
• a non-standard mask that exposes a selected surface of the device is used to form an N ⁇ region that is utilized as part of the JFET transistors, and ions are implanted through the selected surface to form part of the JFET transistors.
• fabrication of the CMOS device of the present invention is completed using standard masks of the baseline CMOS process.
• Figs, la to lp illustrate the fabrication of a device that includes a JFET transistor and is compatible with the normal fabrication process of CMOS devices
• Fig. 2 is a circuit diagram of one embodiment of a differential amplifier that is fabricated according to the process exemplified in figs, la to lp;
• Fig. 3 is a top view of one embodiment of the circuit set forth in Fig. 2.
• Figs, la to lp illustrate the fabrication of a device that includes a JFET transistor and is compatible with the normal fabrication process of CMOS devices. All of the masks and steps illustrated in Figs, la to lp are standard masks and steps used in a standard CMOS fabrication sequence, except for the sequence illustrated in Fig. In which shows the formation of an N-channel within an already formed P-well to create an NJFET transistor.
• Fig. la illustrates a cross-section of the devices at a first stage of their fabrication.
• a p-type wafer was scribed, cleaned, and gettered.
• a pad oxide layer and a nitride layer were formed on top of the wafer.
• the nitride layer was then etched away to expose an area that the N-well may be implanted in.
• a mask is selectively placed on the chip and an N-well implant 60 is formed using phosphorus as a dopant in the region not covered by the mask.
• the wafer is then cleaned and a selective oxide layer 64 is grown which becomes somewhat thicker over the N-well region.
• the nitride layer is then stripped away and a P-well implant 66 is formed using BF 2 as a dopant as shown in Fig. lc.
• Oxide layer 64 is then selectively etched back as shown in Fig. Id.
• Composite pad oxide layer 68 and nitride layer 70 are then formed on the device. The layers are then etched away from desired areas as shown in Fig. le and the device is cleaned.
• a threshold voltage implant not shown, is used to adjust the threshold voltage of transistors formed on the substrate.
• a layer of polysilicon 74 and a mask 76 covering the polysilicon are formed to define the NMOS and PMOS gates.
• a poly etch removes the undesired poly from all regions of the substrate except those over the desired NMOS and PMOS gate regions. The device is then cleaned.
• an oxidation step grows a cap of oxide over the device, and, as shown in Fig. li, a p-type lightly doped drain
• LDD low-density diode
• BF 2 a dopant such as BF 2 .
• the implant is performed over the entire PMOS region of the device and other selected areas by masking all regions that are not desired to be implanted. This implant results in the formation of the source 78 and drain 80 regions of the PMOS transistor and the gate region 90 of the NJFET transistor.
• n-type LDD implant is performed as shown in Fig. lj using a dopant such as phosphorus.
• This implant is performed over the NMOS region of the device, with the PMOS region and other selected regions being masked. This implant results in the formation of the source 92 and drain 94 regions of the NJFET transistor.
• a spacer layer is then formed, not shown, after the device is cleaned, over the wafer and etched back using means well known to those skilled in the art. After the spacer layer is etched away, spacer oxide is left only on exposed sides of the source contacts and drain contacts and the wafer is cleaned. A mask is then placed over the device exposing only the source and drain region of the NJFET transistor. The NJFET source and drain regions 92 and 94, respectively, are then further formed and their resistances lowered by an arsenic implant as shown in Fig. Ik. Next the wafer is cleaned and again subject to oxidation which grows an oxide layer on the polysilicon layer as shown in Fig. 11.
• a mask is placed over the device exposing only the source and drain regions of the PMOS transistor, 78 and 80, respectively, and the gate region 90 of the NJFET transistor.
• the exposed regions are then further formed and their resistances lowered by an implant such as BF 2 .
• Fig. In shows an expanded view of the fabrication process and shows NMOS, PMOS, lateral PNP, and NJFET transistors.
• the expanded view is used in Fig. In because this is the key step in forming an NJFET device during the standard CMOS process.
• NJFET blocking mask 95 is placed over the entire silicon chip except for P-well region 66 in which N-channel JFET 96 is to be formed in.
• N-channel JFET 96 is formed by implanting an N ⁇ element such as phosphorus.
• the use of NJFET mask 95 in this step is the only mask that is not used in the standard CMOS fabrication process.
• NJFET blocking mask 95 allows the formation of N ⁇ region 96 in P-well 66 and protects all other transistor regions from the N ⁇ implant. Formation of N-channel JFET 96 in P-well 66 at this stage does not adversely effect N + regions 92 and 94 or P + region 90 that are already formed in P-well 66.
• the NJFET implant uses phosphorus at a concentration level of about 9 * 10 12 cm -2 and at an energy level of about 150 keV as a dopant to form N ⁇ region 96 which is about at a concentration level of 10 16 cm "3 .
• N-channel 96 is formed, the device is cleaned, and in a manner well known to one skilled in the art, a first dielectric layer 100 is formed on the chip as shown in Fig. lo. Next a first layer of metal is deposited on the device using means well known to those of skill in the art and etched away in desired locations as shown in Fig. lp. Thereafter, additional metalization layers are formed and the device is passivated.
• Fig. 2 is a circuit diagram of one embodiment of a differential amplifier that is fabricated according to the process exemplified in figs, la to lp.
• the differential amplifier shown in Fig. 2 consists of a pair of bipolar transistors 120 and 122, a pair of NJFET transistors 124 and
• Fig. 2 is simply an illustrative example of one of many ways to configure a differential amplifier that are known to those skilled in the art. In no way does Fig. 2 intend to limit the present invention to the single example depicted in the figure.
• the circuit of Fig. 2 receives two input voltages at inputs 140 and 142, respectively, and produces an output voltage at output 144 that is equivalent to the difference in the voltages received at inputs 140 and 142.
• the inputs are coupled to the bases of NJFET transistors 124 and 126, respectively.
• the use of NJFET transistors 124 and 126 at the input stage of the differential amplifier allows for extremely low offset voltage to be realized, and thus, a very accurate differential output.
• the drains of NJFET transistors 124 and 126 are connected to the drain of NMOS transistor 128.
• the gate of NMOS transistor 128 is coupled to receive a biasing voltage at bias input 146.
• the collectors of bipolar transistors 120 and 122 are connected to the sources of NJFET transistors 124 and 126, respectively. While the emitter and base of bipolar transistor 120 are coupled to their respective counterparts on bipolar transistor 122.
• the collector of transistor 122 is connected to the base of transistor 122 in a current mirror fashion, and the output of the differential amplifier is taken at output 144 between the collector of transistor 120 and the source of transistor 124.
• the source of NMOS transistor 128 is coupled to V ss 148, and V cc 150 is coupled to the differential amplifier at a node between the emitters of bipolar transistors 120 and 122.
• Fig. 3 is a top view of one embodiment of the differential amplifier circuit set forth in Fig. 2.
• 128 is an NMOS transistor
• 120 and 122 are a pair of bipolar transistors
• 124 and 126 are a pair of NJFET transistors.
• NJFET transistors 124 and 126 have source regions
• Substrate contact regions 160 surround both NJFET transistors 124 and 126.
• Pins 140 and 142 are inputs to the gates of JFET transistors 124 and 126, respectively, and the output of the differential amplifier is taken at pin 144.
• Pin 146 is coupled to the gate of NMOS transistor 128 to receive the biasing input. While V ⁇ is input at pin 148 and V cc is input at pin 150.
• the differential amplifier can be produced to have a 1 volt threshold voltage, 200 microamp/volt transconductance for a device with a w to 1 ratio of 5, and a breakdown voltage of around 20 volts.
• CMOS process that also creates JFET devices with offset drift on the order of microvolts.
• digital-to-analog converters which use weighted transistors to output a total current, include transistors with proper ratios.
• the implementation of a digital-to-analog converter in the CMOS process of the present invention is advantageous in that once the transistors are created and trimmed to the proper ratio, the ratio will remain unchanged over a period of time because the offset drift will be so low.
• CMOS digital-to-analog converters manufactured according to the present invention will be more accurate than other CMOS digital-to-analog converters.

Landscapes

• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Junction Field-Effect Transistors (AREA)

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Citations (7)

• 1994
  • 1994-02-18 WO PCT/US1994/001990 patent/WO1994019828A1/en not_active Application Discontinuation
  • 1994-02-18 JP JP6519263A patent/JPH08507177A/ja active Pending
  • 1994-02-18 EP EP94909780A patent/EP0686305A1/en not_active Withdrawn
  • 1994-03-08 TW TW083102016A patent/TW232086B/zh active
• 1995
  • 1995-08-25 KR KR1019950703597A patent/KR960701472A/ko not_active Withdrawn

Patent Citations (7)

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