WO1994019828A1

WO1994019828A1 - Fabrication process for cmos device with jfet

Info

Publication number: WO1994019828A1
Application number: PCT/US1994/001990
Authority: WO
Inventors: Richard B. Merrill; Doug R. Farrenkopf
Original assignee: National Semiconductor Corporation
Priority date: 1993-02-25
Filing date: 1994-02-18
Publication date: 1994-09-01
Also published as: KR960701472A; TW232086B; JPH08507177A; EP0686305A1

Abstract

A differential amplifier implemented in baseline CMOS that includes JFET devices, and a process for its fabrication that uses only one more mask than a standard CMOS fabrication process. The differential amplifier has low input current, low offset voltage, and low offset drift.

Description

FABRICATION PROCESS FOR CMOS DEVICE WITH JFET

FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices and their fabrication. More specifically, the present invention relates to fabricating a device in a baseline complementary metal-oxide semiconductor (CMOS) technology using only one extra mask and having very low offset drift.

BACKGROUND OF THE INVENTION

CMOS devices and their fabrication techniques have been well known for many years. CMOS devices have a number of very desirable properties, including extremely low power dissipation, that make their use very attractive for digital circuitry, and thus, they are widely used in integrated circuits.

There is a growing trend in the semiconductor industry, however, towards using mixed signal circuits — circuits that include both digital and analog technology. Entire data collection and data processing systems using linear and digital circuits are now being placed on a single chip. Voltage stability is often very important in these mixed signal circuits. However, when voltage stability is an important consideration, CMOS devices are not competitive with other transistor technologies because of problems with high voltage offset drift.

CMOS devices suffer from high offset drift because current flows at and very near the surface in all CMOS devices. Thus, imperfections in the lattice structure of the silicon substrate near the surface can adversely affect the current flow. Such imperfections are referred to as interface or surface states and occur on integrated circuits where the silicon dioxide layer and silicon substrate meet. Interface states are a direct result of silicon and silicon dioxide having different lattice structures. The different lattice structures of the two materials prevents a perfect bond from forming between the silicon and silicon dioxide layers and results in the formation of interface states. The interface states cause a net charge to form at the interface interfering with current flow and making the threshold voltage difficult to predict.

Offset drift is not a severe problem in pure digital technology because circuits simply need to distinguish between high and low voltage levels. However, offset drift is problem of great significance in many analog applications such as differential amplifiers and analog-to-digital converters. Thus, historically differential amplifiers and like circuits implemented in CMOS performed poorly compared to similar circuits implemented in other technologies such as bipolar technologies or technologies with junction field effect transistors (JFETs) .

Ironically, technological advances in chip processing have actually resulted in CMOS devices having more problems with interface states as generations in technologies progressed. More interface state problems are occurring because technological advances have allowed chip geometries to become smaller and smaller. To achieve the smaller geometries, sophisticated equipment that uses extremely high energy levels during the various baseline CMOS process steps must be used. The increased energy levels result in the presence of a larger number of high energy particles and more plasma damage to the chip. Thus, there is a stronger tendency to damage the interface between the silicon dioxide layer and the silicon substrate when high energy equipment, which is necessary to create chips with smaller feature sizes, is used.

A second problem is that surface states in CMOS devices are unpredictable and difficult to control. Many of the reasons surface states are formed are poorly understood. Often, small, seemingly inconsequential changes during the manufacturing stage can result in changed surface state creation. While the surface states may be easy to control during the pilot stages of production, surface states can become a major problem once actual manufacturing starts.

SUMMARY OF THE INVENTION The present invention seeks to overcome the above problems by creating a device implemented in baseline CMOS technology that has extremely good offset drift and is highly manufacturable. The present invention solves the above problem by creating a CMOS process that includes JFET transistors for reducing drift and that uses only one mask that is not standard to the baseline CMOS process.

The fabrication of the CMOS device of the present invention includes the formation of N-wells, P-wells, field oxide regions, poly interconnections, and N⁺ and P⁺ drain regions on a semiconductor substrate using standard masks of the baseline CMOS process. A non-standard mask that exposes a selected surface of the device is used to form an N~ region that is utilized as part of the JFET transistors, and ions are implanted through the selected surface to form part of the JFET transistors. Finally, fabrication of the CMOS device of the present invention is completed using standard masks of the baseline CMOS process.

The modifications to the baseline CMOS process which result in a CMOS circuit of the present invention are minimal and require the use of only^* a single extra mask. Thus, the present invention allows for a simpler fabrication process and a significant cost savings over prior art devices that required many extra process steps to create JFET devices as part of a CMOS structure. The features and advantages of a CMOS device according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figs, la to lp illustrate the fabrication of a device that includes a JFET transistor and is compatible with the normal fabrication process of CMOS devices; Fig. 2 is a circuit diagram of one embodiment of a differential amplifier that is fabricated according to the process exemplified in figs, la to lp; and

Fig. 3 is a top view of one embodiment of the circuit set forth in Fig. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

CONTENTS I. Fabrication Sequence of CMOS Devices

II. Device Details

I. Fabrication Sequence of CMOS devices

Figs, la to lp illustrate the fabrication of a device that includes a JFET transistor and is compatible with the normal fabrication process of CMOS devices. All of the masks and steps illustrated in Figs, la to lp are standard masks and steps used in a standard CMOS fabrication sequence, except for the sequence illustrated in Fig. In which shows the formation of an N-channel within an already formed P-well to create an NJFET transistor.

Fig. la illustrates a cross-section of the devices at a first stage of their fabrication. Prior to this stage, a p-type wafer was scribed, cleaned, and gettered. Then a pad oxide layer and a nitride layer were formed on top of the wafer. The nitride layer was then etched away to expose an area that the N-well may be implanted in.

Next, as shown in Fig. la, a mask is selectively placed on the chip and an N-well implant 60 is formed using phosphorus as a dopant in the region not covered by the mask. Referring to Fig. lb, the wafer is then cleaned and a selective oxide layer 64 is grown which becomes somewhat thicker over the N-well region. The nitride layer is then stripped away and a P-well implant 66 is formed using BF₂ as a dopant as shown in Fig. lc.

Oxide layer 64 is then selectively etched back as shown in Fig. Id. Composite pad oxide layer 68 and nitride layer 70 are then formed on the device. The layers are then etched away from desired areas as shown in Fig. le and the device is cleaned.

Channel stopping is performed next, as shown in Fig.

If, on the device using a mask to mask the PMOS region and implanting a P-field substance such as boron. This raises the threshold voltage of the parasitic transistors to be formed underneath the oxide layer.

Next the device is cleaned and subject to oxidation which grows a field oxide layer (FOX) 72 on the wafer as shown in Fig. lg. Thereafter, a threshold voltage implant, not shown, is used to adjust the threshold voltage of transistors formed on the substrate.

Referring to Fig. lh, a layer of polysilicon 74 and a mask 76 covering the polysilicon are formed to define the NMOS and PMOS gates. A poly etch removes the undesired poly from all regions of the substrate except those over the desired NMOS and PMOS gate regions. The device is then cleaned.

Next an oxidation step grows a cap of oxide over the device, and, as shown in Fig. li, a p-type lightly doped drain

(LDD) implant is performed using a dopant such as BF₂. The implant is performed over the entire PMOS region of the device and other selected areas by masking all regions that are not desired to be implanted. This implant results in the formation of the source 78 and drain 80 regions of the PMOS transistor and the gate region 90 of the NJFET transistor.

The device is then cleaned again and an n-type LDD implant is performed as shown in Fig. lj using a dopant such as phosphorus. This implant is performed over the NMOS region of the device, with the PMOS region and other selected regions being masked. This implant results in the formation of the source 92 and drain 94 regions of the NJFET transistor.

A spacer layer is then formed, not shown, after the device is cleaned, over the wafer and etched back using means well known to those skilled in the art. After the spacer layer is etched away, spacer oxide is left only on exposed sides of the source contacts and drain contacts and the wafer is cleaned. A mask is then placed over the device exposing only the source and drain region of the NJFET transistor. The NJFET source and drain regions 92 and 94, respectively, are then further formed and their resistances lowered by an arsenic implant as shown in Fig. Ik. Next the wafer is cleaned and again subject to oxidation which grows an oxide layer on the polysilicon layer as shown in Fig. 11.

In Fig. l a mask is placed over the device exposing only the source and drain regions of the PMOS transistor, 78 and 80, respectively, and the gate region 90 of the NJFET transistor. The exposed regions are then further formed and their resistances lowered by an implant such as BF₂.

Fig. In shows an expanded view of the fabrication process and shows NMOS, PMOS, lateral PNP, and NJFET transistors. The expanded view is used in Fig. In because this is the key step in forming an NJFET device during the standard CMOS process. In Fig. In, NJFET blocking mask 95 is placed over the entire silicon chip except for P-well region 66 in which N-channel JFET 96 is to be formed in. N-channel JFET 96 is formed by implanting an N~ element such as phosphorus. The use of NJFET mask 95 in this step is the only mask that is not used in the standard CMOS fabrication process. NJFET blocking mask 95 allows the formation of N~ region 96 in P-well 66 and protects all other transistor regions from the N~ implant. Formation of N-channel JFET 96 in P-well 66 at this stage does not adversely effect N⁺ regions 92 and 94 or P⁺ region 90 that are already formed in P-well 66. In the preferred embodiment of the present invention, the NJFET implant uses phosphorus at a concentration level of about 9 * 10¹² cm^-2 and at an energy level of about 150 keV as a dopant to form N~ region 96 which is about at a concentration level of 10¹⁶cm^"3.

After N-channel 96 is formed, the device is cleaned, and in a manner well known to one skilled in the art, a first dielectric layer 100 is formed on the chip as shown in Fig. lo. Next a first layer of metal is deposited on the device using means well known to those of skill in the art and etched away in desired locations as shown in Fig. lp. Thereafter, additional metalization layers are formed and the device is passivated.

II. Device Details

Fig. 2 is a circuit diagram of one embodiment of a differential amplifier that is fabricated according to the process exemplified in figs, la to lp. The differential amplifier shown in Fig. 2 consists of a pair of bipolar transistors 120 and 122, a pair of NJFET transistors 124 and

126, and a NMOS transistor 128. The differential amplifier of Fig. 2 also has two inputs, 140 and 142, an output 144, and a bias input 146. Fig. 2 is simply an illustrative example of one of many ways to configure a differential amplifier that are known to those skilled in the art. In no way does Fig. 2 intend to limit the present invention to the single example depicted in the figure.

The circuit of Fig. 2 receives two input voltages at inputs 140 and 142, respectively, and produces an output voltage at output 144 that is equivalent to the difference in the voltages received at inputs 140 and 142. The inputs are coupled to the bases of NJFET transistors 124 and 126, respectively. The use of NJFET transistors 124 and 126 at the input stage of the differential amplifier allows for extremely low offset voltage to be realized, and thus, a very accurate differential output.

The drains of NJFET transistors 124 and 126 are connected to the drain of NMOS transistor 128. The gate of NMOS transistor 128 is coupled to receive a biasing voltage at bias input 146. The collectors of bipolar transistors 120 and 122 are connected to the sources of NJFET transistors 124 and 126, respectively. While the emitter and base of bipolar transistor 120 are coupled to their respective counterparts on bipolar transistor 122. The collector of transistor 122 is connected to the base of transistor 122 in a current mirror fashion, and the output of the differential amplifier is taken at output 144 between the collector of transistor 120 and the source of transistor 124. Finally, the source of NMOS transistor 128 is coupled to V_ss 148, and V_cc 150 is coupled to the differential amplifier at a node between the emitters of bipolar transistors 120 and 122.

Fig. 3 is a top view of one embodiment of the differential amplifier circuit set forth in Fig. 2. For convenience, the same reference numerals used in Fig. 2 are used in Fig. 3 to refer to like elements. In Fig. 3 128 is an NMOS transistor, 120 and 122 are a pair of bipolar transistors, and 124 and 126 are a pair of NJFET transistors. NJFET transistors 124 and 126 have source regions

90, gate regions 92, and drain regions 94 as functional components. Substrate contact regions 160 surround both NJFET transistors 124 and 126. Pins 140 and 142 are inputs to the gates of JFET transistors 124 and 126, respectively, and the output of the differential amplifier is taken at pin 144. Pin 146 is coupled to the gate of NMOS transistor 128 to receive the biasing input. While V_ββ is input at pin 148 and V_cc is input at pin 150.

Using the fabrication sequence of figs, la to lp and described in the accompanying text, it is possible to produce a differential amplifier like the one embodied in figs. 2 and 3 in a 0.5 micron process that has offset drift on the order of microvolts. Furthermore, the differential amplifier can be produced to have a 1 volt threshold voltage, 200 microamp/volt transconductance for a device with a w to 1 ratio of 5, and a breakdown voltage of around 20 volts.

The fabrication sequence discussed above is not limited to differential amplifiers. Those of skill in the art will recognize many applications that would benefit from having a CMOS process that also creates JFET devices with offset drift on the order of microvolts. For instance, it is important that digital-to-analog converters, which use weighted transistors to output a total current, include transistors with proper ratios. The implementation of a digital-to-analog converter in the CMOS process of the present invention is advantageous in that once the transistors are created and trimmed to the proper ratio, the ratio will remain unchanged over a period of time because the offset drift will be so low. Thus, CMOS digital-to-analog converters manufactured according to the present invention will be more accurate than other CMOS digital-to-analog converters.

It is to be understood that the above description is intended to be illustrative and not restrictive. Many variations of the invention will become apparent to those of skill in the art upon review of this disclosure. Merely by way of example, particular regions of the devices shown herein have been illustrated as being p-type or n-type, but it will be apparent to those of skill in the art that the role of n-type and p-type dopants may readily be reversed. Further, while the invention has been illustrated with regard to specific dopant concentrations and energy levels in some instances, it should also be clear that a wide range of dopant concentrations and energy levels may be used for many features of the devices herein without departing from the scope of the inventions herein. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.

Claims

WHAT IS CLAIMED IS;

1. An improved method for forming a CMOS mixed signal device fabricated in a semiconductor substrate having a major surface utilizing a standard baseline set of CMOS masks and that includes JFET transistors, said method comprising the steps of: forming N-wells, P-wells, field oxide regions, poly interconnections, and N⁺ and P⁺ drain regions included in said CMOS device using standard masks of the baseline CMOS process; using a non-standard mask to expose only a selected surface of the semiconductor substrate that overlies an N~ region to be utilized as part of the JFET transistors; implanting ions through said selected surface to form a part of said JFET transistor; utilizing the standard masks of the baseline CMOS process to complete the fabrication of the CMOS device.

2. The method of claim 1 wherein said selected surface includes a P-well in which said N^" region is to be formed.

3. The method of claim 2 wherein N⁺ JFET source and drain regions and a P⁺ JFET gate region are formed in said N~ region utilizing the standard masks of the baseline CMOS process.

4. The method of claim 1 wherein said CMOS device is a differential amplifier having an N-channel JFET transistor for receiving input signals.

5. The method of claim 1 wherein said ions implanted through said selected surface to form said part of said JFET transistor are phosphorus ions.

6. A method of fabricating field effect devices on a semiconductor substrate comprising the steps of: (a) forming an insulator region on a surface of a semiconductor substrate;

(b) forming a mask on a portion of said semiconductor substrate, said mask defining an N-well region on said substrate;

(c) implanting said semiconductor device with an N~ dopant to form an N-well;

(d) forming a mask on a portion of said semiconductor substrate, said mask defining a P-well region on said substrate;

(e) implanting said semiconductor device with a P^" dopant to form a P-well;

(f) forming a polysilicon layer on said insulator region; (g) forming a mask on portions of said polysilicon layer, said portions defining gate regions of field effect devices; (h) implanting said semiconductor device with an N⁺ dopant to form N⁺ regions in said P-well; (i) implanting said semiconductor device with a P⁺ dopant to form P⁺ regions is said N-well and a P⁺ region in said P-well; (j) implanting said semiconductor device with an N" dopant to form an N-channel in said P-well so that said N⁺ regions in said P-well are in said N-channel and said P⁺ region in said P-well is in said N-channel; (k) forming a conductive region along said surface; and (1) etching said conductive region to form desired contacts.

7. A differential amplifier fabricated in a semiconductor substrate having a major surface, said differential amplifier fabricated by using a standard baseline set of CMOS masks and process steps and that comprises: an NJFET transistor constructed on the major surface of the semiconductor substrate by adding a non-standard mask that masks the entire semiconductor substrate except for a selected NJFET region to be utilized as part of said NJFET transistor and implanting ions through said selected NJFET region to form a part of said NJFET transistor, wherein said NJFET transistor is for receiving input signals to said differential amplifier.