JPH05226588A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To easily realize a mixed circuit wherein several kinds of different transistors have been formed on the same substrate by a method wherein several processes are added to the manufacturing method of a bipolar transistor or a MOS transistor J-FET. CONSTITUTION:An n-well 63 is formed on a P-type substrate 61 or a deep well by using a mask 62. A shallow well is formed in it. Then, a field oxide film 65 is formed. By making use of it as a mask, ions are implanted into a channel 66 for a MOS transistor. In addition, a gate oxide film 69 is formed; after that, an emitter diffusion window 70 is opened in the gate oxide film 69 in a bipolar transistor. After that, a gate electrode 71 is formed. In succession, a heat treatment is executed; an emitter is formed. Tons are implanted into a channel region 67 for a J-FET, a bipolar base region 68, a channel region for a depletion transistor and a deep channel region for a composite-channel transistor which are tilted at a large angle with reference to the surface of a wafer; after that, a heat treatment is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a MIS (metal insulating film semiconductor) type, MOS (metal oxide film semiconductor) type semiconductor device or junction type field effect semiconductor having a high function. (J-FET)
And bipolar semiconductor devices and a method of manufacturing the same.

[0002]

2. Description of the Related Art In semiconductor devices (devices), especially semiconductor devices using MOS transistors, further miniaturization and higher speed are required due to higher system performance and larger capacity. As a result, an element having a size of 1 μm or less has been put into practical use. At this time, the element structure is not the same as before,
New structures and more complex manufacturing processes have been adopted to respond to miniaturization.

For example, with miniaturization, it is necessary to thin the gate oxide film. As a result, the impurity concentration near the channel becomes high, and the concentration of the semiconductor substrate (or well region) also rises due to the miniaturization of the isolation region. Since the gate length becomes shorter, a large electric field is generated near the PN junction near the drain. Hot carriers (charged particles with large energy, often called electrons because they are electrons) generated by the electric field jump into the gate oxide film and TDDB (Time D
ependent dielectric Break-down, which is a time-dependent destruction, that is, a phenomenon that gradually deteriorates instead of sudden destruction) occurs.

FIG. 17 shows the structure of a conventional MOS transistor. FIG. 17 (a) is a top view and FIG. 17 (b) is FIG.
It is sectional drawing in AA 'of (a).

A well 2 is formed in a semiconductor substrate 1, and a gate electrode 5 and a source / drain 6 are formed on a gate oxide film 4 in a transistor region in the well 2 separated by a field oxide film 3. 7 is a channel.

A MOS transistor is easy to integrate and consumes less power when it has a CMOS (complementary MOS) transistor structure. The speeding up (operating frequency), which has been a problem in the past, has also been improved by miniaturization.

[0007]

However, the above-mentioned conventional M
In the OS transistor, it is more advantageous to use a bipolar transistor for the input / output portion. For this reason, in ASICs (ICs for specific applications) and dedicated LSIs, it is required that the CMOS transistors have an internal circuit configuration and that bipolar transistors be used as input / output portions.

The operating principle of the MOS transistor is the electric field effect of the gate electrode insulated by the gate oxide film (insulating film). Therefore, the deterioration of the characteristics of the gate oxide film has become a serious problem.

That is, since the gate length is shorter, a large electric field is generated near the PN junction near the drain. Hot carriers generated by the electric field jump into the gate oxide film, causing deterioration in transistor characteristics.

In certain circuits, it may be more advantageous to combine a MOS transistor and a bipolar transistor. For example, Nikkei Electronics 1989
It has been proposed to construct a SRAM (STATIC RANDAM ACCESS MEMORY) with a P-channel MOS transistor and an NPN bipolar transistor, which are introduced on Feb. 20, pp. 283-285.

[0011]

The present invention has been made in order to solve the above-mentioned problems caused by miniaturization and high functionality, and is manufactured by the same manufacturing method as that of a MOS transistor.
By forming an element having a function not present in FETs, bipolar transistors, and conventional transistors, the structure of the circuit is facilitated, and the circuit area is reduced while improving the function of the element.

The J-FET has not been used so much because it cannot be miniaturized so far. However, since there is no gate insulating film of the MOS transistor, there is little risk of deterioration due to a high electric field, and if the transistor is a small size, it is a MO transistor.
It has advantages over S-transistors. MO if required
It is also possible to form the channel of the S-transistor and the channel of the J-FET together to form a compound transistor (hereinafter abbreviated as compound channel transistor) intermediate between the two transistors. Since this composite channel transistor has two control terminals of the gate electrode of the MOS transistor and the gate electrode of the J-FET, it can be used for multi-valued logic.

Further, as described above, the bipolar transistors of the same size in the input / output portion are advantageous because they can pass a larger current.

Therefore, it is necessary to form the J-FET and the bipolar transistor by adding as few steps as possible to the conventional MOS transistor manufacturing method. Some key points for this are shown below.

(1) In order to form a J-FET or a bipolar transistor, the well has a double structure. This makes it possible to form a shallow well by a highly accelerated ion implantation technique and also has an effect of reducing the distance between wells.

(2) The channel of the J-FET and the intrinsic base of the bipolar transistor are formed before and after the channel formation of the MOS transistor, and the boundary between the source / drain and the base region is the gate electrode (polycrystalline silicon) like the MOS transistor. Is used as an ion implantation mask in a self-aligned manner. This makes it possible to miniaturize the J-FET and the bipolar transistor.

(3) The emitter of the bipolar transistor diffuses impurities from the polycrystalline silicon used as the gate electrode by forming an opening in the gate oxide film of the MOS transistor in advance. After that it is possible to spread).

[0018]

According to the method of manufacturing a semiconductor device of the present invention, a bipolar transistor, a J-FET, and a MOS transistor can be realized by adding a few steps to the conventional method of manufacturing a MOS transistor. This makes it possible to easily realize a circuit in which transistors of different types are mixed.

According to the present invention, a "composite channel transistor" having two channels of a J-FET and a MOS transistor can be formed. Therefore, by forming an element having a function that is not present in a transistor, a circuit configuration can be facilitated, and a circuit area can be reduced while improving the function of the element.

[0020]

1 shows the structure of a composite channel transistor according to an embodiment of the present invention.

FIG. 1 (a) is a plan view of the composite channel transistor, and FIG. 1 (b) is a sectional view taken along the line BB 'of FIG. 1 (a).

In FIG. 1, a shallow well 12 is formed in a semiconductor substrate 11 or a deep well. This shallow well 12 is the junction gate 13 of the composite channel transistor. The source / drain 14 of the MOS transistor, the junction gate 13, and the insulated gate 15 are separated by a field oxide film 16. The insulated gate 15 is formed on the gate insulating film 19. As the channel, a junction gate channel 17 and an insulated gate channel 18 are formed together.

FIG. 2 shows a J-FE according to an embodiment of the present invention.
The structure of T is shown. 2A is a plan view of the J-FET, and FIG. 2B is a sectional view taken along the line CC ′ of FIG.

In FIG. 2, a shallow well 22 is formed in a semiconductor substrate 21 or a deep well. This shallow well 22 serves as a junction gate 23 of the composite channel transistor. The source / drain 24, the junction gate 23, and the insulated gate 25 are separated by a field oxide film 26. Insulated gate 15 is gate insulating film 1
9 is formed. As for the channel, only the channel 27 of the junction gate is formed. Insulated gate 2 in this case
No. 5 is not electrically connected because the purpose is to form channels in a self-aligned manner. Further, it may be removed after it is used as a mask for source / drain implantation.

FIG. 3 shows the structure of a bipolar transistor. 3A is a plan view of the bipolar transistor, and FIG. 3B is a sectional view taken along the line DD ′ of FIG.

In FIG. 3, a shallow well 32 is formed in a semiconductor substrate 31 or a deep well. This shallow well 32 is the collector 3 of the bipolar transistor.
It is 3.

The external base 34, the emitter 35, and the collector 33 are separated by a field oxide film 36. The intrinsic base 37 is formed only in the masked region of the emitter 35. The rest is the external base 34.

Although the emitter 35 is described as being surrounded by the external base 34, the emitter 35 may be in contact with the field oxide film 36.

In the emitter 35, by forming the opening of the gate oxide film 39 in advance, the emitter 35 is also diffused when the gate electrode (polycrystalline silicon) is diffused (polycrystalline silicon emitter).

The bipolar transistor is often of the npn type, but the diffusion of polycrystalline silicon may be of the n type only. If necessary, it is possible to selectively use n-type and p-type polycrystalline silicon.

FIG. 4 shows the structure of the enhancement MOS transistor. Figure 4 (a) shows the enhancement MOS
FIG. 4A is a plan view of the transistor, and FIG.
FIG.

In FIG. 4, a shallow well 42 is formed in a semiconductor substrate 41 or a deep well. In this explanatory view, electrical extraction of the shallow well 42 is omitted.

The source / drain 44 and the insulated gate 45 are separated by a field oxide film 46. The insulated gate 45 is formed on the gate insulating film 49. The channel is only the insulated gate channel 48.

FIG. 5 is a sectional view showing the structure of a depletion MOS transistor. Depletion MOS
The transistor is a transistor that is always set to the on state regardless of the gate voltage.

FIG. 5 (a) is a plan view of the depletion MOS transistor, and FIG. 5 (b) is FF 'in FIG. 5 (a).
FIG.

In FIG. 5, a shallow well 52 is formed in a semiconductor substrate 51 or a deep well. In this explanatory view, electrical extraction of the shallow well 52 is omitted.

The source / drain 54 and the insulated gate 55 are separated by the field oxide film 56, and the insulated gate 55 is formed on the gate insulating film 59. In addition to a channel 58 of an insulated gate, a channel 57 of a diffusion layer of the same type as the source / drain is formed.

In these semiconductor devices, a case will be described in which a deep n well is formed on a p type semiconductor substrate and a shallow p well is formed therein.

In the shallow p well, an npn bipolar transistor, an n channel J-FET and an n channel MOS are provided.
A transistor and an n-channel composite channel transistor are formed.

The depletion MOS transistor is different from the normal one in the terminal for taking out the well voltage. That is, by integrating a plurality of transistors in a shallow well, the well voltage extraction terminal is only a common terminal.

Similarly, if a deep p-well is formed on a p-type semiconductor substrate and a shallow n-well is formed therein, a pnp bipolar transistor, a p-channel J-FET, a p-channel MOS transistor and a p-channel composite channel transistor are formed. It is formed. At this time, since the deep p-well is of the same type as the semiconductor substrate, it may be formed on the semiconductor substrate if only normal transistors are formed.
Further, when the semiconductor substrate is an n-type semiconductor substrate, the same treatment can be performed by replacing the p-type and the n-type described above with n-type and p-type, respectively.

6 to 10 are sectional views showing respective steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, the n-well 6 is formed on the p-type semiconductor substrate 61 or on the deep well using a mask 62 of a predetermined pattern.
3 is formed (FIG. 6).

A shallow p well 64 is formed in the n well 63 according to a predetermined pattern (FIG. 7). At this time, a shallow n well may be formed between the p wells 64.

Next, a field oxide film 65 is formed.
Using the field oxide film 65 as a mask, ions are implanted into the channel 66 of the MOS transistor (FIG. 8).

Here, FIG. 11 is an impurity concentration distribution diagram showing the impurity distribution in the channel portion of each functional element.

The impurity distribution in the channel portion is shown in FIG.
As shown in (a), (b), (c), and (d), in the composite channel transistor, J-FET, and bipolar transistor, one or a plurality of pn junctions are formed in the channel region and the emitter-base region. Has been done. On the other hand, in a surface channel enhancement type MOS transistor, no junction is formed in the channel portion. In the buried channel type or depletion type transistor, one pn junction is formed in the channel portion.

Further, after forming the gate oxide film 69,
The bipolar transistor has an emitter diffusion window 70 opened in the gate oxide film 69. Then, the gate electrode 71 is formed (FIG. 9). Although the gate electrode 71 is made of polycrystalline silicon or the like, the impurity diffusion may be performed by either simultaneously growing the film while diffusing it or by diffusing it after the growth.

After that, through a heat treatment process, impurities are diffused from the gate electrode on the emitter which is the emitter electrode 72, and the emitter 73 is formed (FIG. 10).

The extrinsic base and the intrinsic (active) base are
It has not yet formed at this point.

The channel region 67 of the J-FET, the base region 68 of the bipolar transistor, the channel region of the depletion transistor, and the deep channel region of the composite channel transistor are formed by ion implantation.
Ion implantation is performed by inclining a large angle with respect to the surface of the wafer to implant ions under the gate electrode 71 and the emitter electrode 72, which serve as a mask, and then perform heat treatment.

In this embodiment, the ion implantation angle is 45 degrees, but it can be set arbitrarily within the range of 10 degrees to 80 degrees.

Since the ion implantation is performed with a tilted angle, it is necessary to repeatedly perform the ion implantation under the same conditions, for example, from four directions so as to prevent the characteristics of the transistor from varying depending on the implantation angle.

The implantation amount is 5 × 10 ¹² cm ⁻³ to 2 × 10 ¹³ cm ⁻³ per direction, and the implantation is performed from four directions. The acceleration energy is 20 to 60 keV for boron (B) ions and 40 to 100 keV for phosphorus (P) ions.

This state will be described with reference to FIG. Figure 1
2 shows a state in which ions are implanted under the polycrystalline silicon serving as a mask, and the semiconductor substrate 81 or
A gate oxide film 82 is formed on the well, and polycrystalline silicon that will become the gate electrode 83 is further grown. FIG. 12 shows a state in which this is thereafter etched according to a predetermined pattern. The gate electrode 83 serves as a mask for oblique ion implantation.

FIG. 12A shows a case where the pattern of the gate electrode 83 is relatively wide, and the ion-implanted layer 84 is obliquely implanted.
Does not contact between the source and drain.

In the ion implantation layer 84, the solid line shows the impurity distribution boundary (pn junction) immediately after the ion implantation. The broken line shows the impurity distribution boundary (pn
It is a joint).

FIG. 12B shows the impurity distribution when the pattern of the gate electrode 83 is relatively narrow. The ion-implanted layer 84 obliquely implanted is not in contact immediately after the implantation (shown by a solid line). By the subsequent heat treatment, the ion implantation layers 84 on both ends of the gate electrode 83 come into contact with each other (shown by the broken line).

It is also possible to intentionally use an implantation angle at which ion channeling easily occurs. The configurations of the various transistors thus formed correspond to the semiconductor device shown in FIGS.

Next, the characteristics of the composite channel transistor will be described. The composite channel transistor operates as a normal MOS transistor or a J-FET when two gates are used independently, but it can also be operated as a combination of two gates.

Since three states can be taken in this way, it is possible to operate as multi-valued logic. Table 1 shows an example of the operation of the composite channel transistor as multi-valued logic.

[0062]

[Table 1]

The names in the upper row of Table 1 represent the characteristics of the composite channel transistor. The column on the left shows the switching state during operation of the name representing the characteristic.

Further, in the composite channel transistor, the drain current tends to increase even when viewed only from the operation of the normal MOS transistor.

In FIG. 13, semiconductor substrate 90, gate electrode 91, gate insulating film 92, source 94, drain 9
Set to 4.

In a normal MOS transistor operating state in which the gate potential of the J-FET, which is the semiconductor substrate or the shallow well 90, is fixed to the same potential as the source 93, the gate electrode 91 has a gate voltage higher than the threshold value. Is applied to the drain current, the drain current gradually increases. With the increase, hot carriers 96 are generated, and the gate insulating film 9
Jump into 2. The hot carriers 96 generate a gate current 97 and a substrate current 98 flowing in the semiconductor substrate (well 90).
Becomes Since the substrate current 98 raises the potential of the semiconductor substrate 90, the potential of the gate of the J-FET is raised.

Assuming that the threshold voltage of the J-FET is 0.5
Assuming V, the substrate current 98 causes the semiconductor substrate 9
0 or the potential near the J-FET channel is 0.5
When the voltage exceeds V, the channel of the J-FET is turned on. Therefore, the drain current increases.

That is, as shown in FIG. 13, the composite channel transistor can pass a current about 1.2 to 3 times that of a MOS transistor of the same size.

FIG. 14 is a characteristic diagram comparing the conventional MOS transistor with the composite channel transistor of the present invention.

When hot carriers 96 are generated from this, the channel of the J-FET is turned on. This reduces the current flowing through the channel portion of the MOS transistor. Therefore, the gate current that jumps into the gate insulating film 92 and deteriorates the characteristics is smaller than that of a normal MOS transistor, and the life is extended.

FIG. 15 shows an equivalent circuit of the composite channel transistor. The drain and the source of the MOS transistor and the J-FET are common, and the substrate of the MOS transistor is the gate of the J-FET. This composite channel transistor, like a thyristor, has an M
When the OS transistor is turned on, the J-FET is turned on by the substrate bias generated by the substrate current. In this state, the drain current flows unless the potential of the substrate changes (it returns to the original at some time due to the leakage of the substrate).

Further, as shown in FIG. 16, it can also be used as a dynamic memory cell. In the example of FIG. 16, a semiconductor substrate or a deep well and a shallow well, such as J-FE, is used.
Charge is accumulated by utilizing the junction capacitance between the gate of T and the gate.

Previously proposed semiconductor elements (Japanese Patent Laid-Open No. Hei 3 (1999) -312058)
-151661) is similar in configuration.

In the structure and manufacturing method, the J-FET, the channel portion of the composite channel transistor, and the intrinsic (active) base of the bipolar transistor were formed before the gate electrode was formed and before and after the threshold control implantation. The present invention is different in that it is formed by oblique ion implantation after forming the gate electrode.

The advantages of the present invention are as follows.
In the case of a bipolar transistor, the process can be simplified because an intrinsic base and an external base can be formed at the same time.

Different impurity distributions can be formed when oblique ion implantation is performed using the gate electrode as a mask, as compared with the case where ion implantation is performed on the entire active region before forming the gate electrode.

In the case of a bipolar transistor or J-FET, it is involved in the formation of a base or a channel which has a great influence on the characteristics.

For this reason, it is only necessary to select a manufacturing method that can obtain predetermined characteristics in accordance with the size of the transistor and the setting of heat treatment in the process.

In the embodiment of the present invention, the case where all the transistors having the five structures are formed on the same semiconductor substrate has been described. The same applies to the case where one of the five transistors is formed.

[0080]

As described above, according to the present invention, a composite channel transistor having two channels, J-FE, is obtained by improving the conventional method for manufacturing a MOS transistor.
Since T and bipolar transistors can be formed on the same semiconductor substrate, a circuit in which different types of transistors are mixed can be easily realized.

Since a composite channel transistor having two channels of a J-FET and a MOS transistor can be formed, it is possible to form an element having a function which has not been found in conventional transistors. In addition, while simplifying the circuit configuration and improving the device function and hot carrier resistance,
The circuit area can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a composite channel transistor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a J-FET according to an embodiment of the present invention.

FIG. 3 is a configuration diagram showing a structure of a bipolar transistor.

FIG. 4 is a configuration diagram showing a structure of an enhancement MOS transistor.

FIG. 5 is a block diagram showing the structure of a depletion MOS transistor.

FIG. 6 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step in the semiconductor device fabrication method of the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the embodiment of the present invention.

FIG. 11 is an impurity concentration distribution diagram showing the impurity distribution in the channel portion of each functional element of the present invention.

FIG. 12 is a cross-sectional view showing a state of oblique ion implantation according to the present invention.

FIG. 13 is a cross-sectional view showing the operation of the composite channel transistor of the present invention.

FIG. 14 is a characteristic diagram comparing the composite channel transistors of the present invention.

FIG. 15 is an equivalent circuit diagram of the composite channel transistor of the present invention.

FIG. 16 is an equivalent circuit diagram when the composite channel transistor of the present invention is used in a memory cell.

FIG. 17 is a sectional view showing the structure of a conventional MOS transistor.

[Explanation of symbols]

11, 21, 31, 41, 51 Semiconductor substrate (or deep well) 12, 22, 32, 42, 52 Shallow well 13,23 Junction gate 14, 44, 54 Source / drain 15, 25, 45, 55 Insulated gate 16 , 26, 36, 46, 56 Field oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9171-4M H01L 29/80 C

Claims (3)

[Claims] 1. A shallow well having a semiconductor substrate of one conductivity type, a shallow well having a terminal for extracting an electric potential of an opposite conductivity type, which is formed on the semiconductor substrate of the one conductivity type and separated for each element, and each shallow well. A junction field effect semiconductor device having one element formed and a first channel of a metal insulating film semiconductor element formed in contact with an insulating film for each one conductivity type element, and a diffusion layer of one conductivity type And a second channel of
A semiconductor device, wherein the terminal is connected by a wiring different from the source of the metal insulating film semiconductor element. 2. A shallow well having a semiconductor substrate of one conductivity type, a shallow well having a terminal for extracting an electric potential of an opposite conductivity type, which is formed on the semiconductor substrate of the one conductivity type and separated for each element, and each shallow well. One element is formed, and a first channel of a metal insulating film semiconductor element formed in contact with an insulating film for each one conductivity type element, and one conductivity type diffusion layer by a plurality of oblique ion implantations. And a channel of a junction field effect semiconductor element and an external base and an active base of a bipolar semiconductor element, or a channel of a depletion-type metal insulating film semiconductor element. 3. The channel of the junction field effect semiconductor device and the base of the bipolar semiconductor device are simultaneously formed on the semiconductor substrate and have a depth different from the channel of the metal insulating film semiconductor device. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed.