JP3059009B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is used for driving a display tube and has a high driving capability and a high withstand voltage, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more sophisticated, semiconductor devices having high driving capability and withstand voltage have been demanded. In particular, a high withstand voltage semiconductor device provided at an output terminal of a microcomputer for driving a display tube has a high driving capability and high performance without impairing the characteristics of a logic circuit portion in the same chip realized by fine processing technology. It must be pressure resistant.

FIG. 6 is a sectional view of a conventional semiconductor device.
In FIG. 6, a semiconductor substrate 1 made of N-type silicon
An insulating film 2 is formed thereon. On this insulating film 2, a polysilicon gate electrode 3 is formed. Also,
The offset region 4 is a P-type medium concentration diffusion region formed in the semiconductor substrate 1 located on one side of the gate electrode 3. Further, the drain 5 is a P-type high-concentration diffusion region formed in the semiconductor substrate 1 facing the gate electrode 3 via the offset region 4. In addition, source 6
Is the semiconductor substrate 1 located on the other side of the gate electrode 3
This is a P-type high-concentration diffusion region formed therein.

The operation of the above configuration will be described below. First, when a high voltage is applied to the drain 5 in a state where the semiconductor device is off, a depletion layer spreads in the offset region 4. As a result, a voltage drop substantially equal to the high voltage applied to the drain 5 occurs. As a result, the voltage applied to the PN junction between the semiconductor substrate 1 and the offset region 4 under the gate electrode 3, which is one place defining the breakdown voltage of the semiconductor device, is reduced. As a result, a high breakdown voltage semiconductor device is realized. In order to increase the breakdown voltage, the depletion layer must be sufficiently widened. Therefore, it is necessary to reduce the impurity concentration of the offset region 4 or increase the length of the offset region 4.

On the other hand, when the semiconductor device is conducting, a current flows from the source 6 to the drain 5 via the offset region 4. At this time, the offset region 4 functions as a parasitic resistance. In order to increase the driving capability of the semiconductor device, it is necessary to lower the resistance value. Therefore, it is necessary to increase the impurity concentration of the offset region 4 or shorten the length of the offset region 4.

That is, the relationship between the driving capability and the breakdown voltage is in a trade-off relationship such that the breakdown voltage decreases when the driving capability is improved, and the driving capability decreases when the breakdown voltage is improved.
Therefore, it is necessary to appropriately set the impurity concentration and length of the offset region 4 in order to obtain high driving capability and high withstand voltage.

[0007] The location that defines the breakdown voltage of the semiconductor device is the point E of the PN junction near the boundary between the drain 5 and the offset region 4 or the point F of the PN junction at the end of the offset region 4 below the gate electrode 3. . When a high voltage is applied to the drain 5, the electric field intensity reaches 30 V / μm or more at either the point E or the point F at the earliest, and the PN junction there breaks down.
According to the study of the present inventors, when the concentration of the semiconductor substrate 11 and the offset region 14 is appropriately controlled, when the length of the offset region 14 is 2 to 3 μm or more, the point E defines the breakdown voltage of the entire semiconductor device. I know that.

FIG. 7 is a diagram showing the impurity distribution in the line segment AB and the line segment CD shown in FIG. 6. Since the impurity distribution in the high concentration portion of the drain 5 and the source 6 is the same, the line segment CD is evident, so the source 6 Chosen on the side. 7, a characteristic M indicated by a solid line indicates an impurity distribution in a line segment AB in the offset region 4, and a characteristic N indicated by a dotted line indicates a line segment CD in the source 6.
The impurity concentration is medium in the offset region 4 and high in the drain 5 and the source 6. The offset region 4 is formed by one-time ion implantation and thermal diffusion at a modest temperature. Therefore, the impurity concentration of the offset region 4 at the point E in FIG. 6 is low. Therefore, the impurity distribution here becomes steep. As a result, the electric field strength is increased, and defines the withstand voltage of the entire semiconductor device.

Conventionally, a semiconductor device having a gate electrode 3 having a length of 4 μm, an offset region 4 having a length of 4 μm, a withstand voltage of about −60 V, and a drain current of about −15 μA / μm has been realized.

Next, a conventional method for manufacturing a semiconductor device will be described. FIG. 8 is a sectional view showing each step of the manufacturing method in the semiconductor device of FIG. First, as shown in FIG. 8A, an insulating film 2 is formed on a surface of a semiconductor substrate 1 by using a silicon oxide film or the like. Further, a gate electrode 3 made of polysilicon or the like is formed on the insulating film 2. Here, the semiconductor substrate 1 is made of N-type silicon, and has an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁵ c in order to realize a sufficiently large withstand voltage.
m ⁻³ . The lower the impurity concentration of the semiconductor substrate 1, the higher the breakdown voltage. However, the impurity concentration that can be formed stably and inexpensively including the logic circuit portion in the same chip is within the above range.

Next, as shown in FIG. 8B, using the gate electrode 3 as a mask, boron (B ⁺ ) is applied only once at an acceleration energy of about 50 KeV, a dose of about 1.5 × 10 ¹² cm ⁻² , and so on. The offset region 4 'is formed by ion implantation. At this time, since the acceleration energy is small, boron (B ⁺ ) does not penetrate through the gate electrode 3 and enter the channel region located between the drain 5 and the source 6.

Further, as shown in FIG. 8C, a part of the gate electrode 3 and the offset region 4 are covered with a resist 7, and
F ₂ is ion-implanted to form a drain 5 and a source 6. Then, to improve the breakdown voltage, the offset region 4
In some cases, heat treatment is performed for the purpose of smoothing the impurity concentration distribution in the substrate depth direction. However, when the logic circuit part realized by the fine processing technology is in the same chip,
If the heat treatment is performed at a high temperature for a long time, the characteristics of the logic circuit part will be impaired.

The same structure as the semiconductor device shown in FIG. 6 and FIG. Toshiaki Mashara, Masaharu Kubo "Device Design of An Ion Implanted
High Voltage Mos F E T "(I.Y.
oshida, T .; Masuhara, and M.S. K
ubo "Device Design of I
on Implanted High Voltage
MOSFET ", Proceedings of
the 6th Conference Soli
d State Devices, p. 249 −255, 19
74). In this document, offset region 4
Has an impurity concentration of 7 × 10 ¹⁴ cm ⁻³ . The manufacturing conditions are such that boron is ion-implanted only once into the semiconductor substrate at an acceleration energy of 30 to 100 KeV and a dose of about 6 × 10 ¹¹ cm ⁻² . Thereby, a withstand voltage of 150 V is achieved. However, the length of the gate electrode 3 is 12 μm and the length of the offset region 4 is 5 μm, which is very large. Further, annealing at 950 ° C., which is a high-temperature heat treatment, must be performed. With this method, it is difficult to obtain a semiconductor device having a high driving capability and a high withstand voltage with a small occupation area corresponding to the logic circuit portion realized by the fine processing technology. Will be lost.

[0014]

As described above, in the conventional semiconductor device and the method of manufacturing the same, when the impurity concentration of the offset region 4 is increased for higher driving capability, the withstand voltage is reduced. Therefore, when the impurity concentration of the offset region 4 is reduced, the driving capability is reduced, and when the heat treatment is added, the characteristics of the logic circuit portion are deteriorated.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems and provides a semiconductor device having a high driving capability and a high withstand voltage with a small occupation area corresponding to a fine processing technology without impairing the characteristics of a logic circuit portion and a method of manufacturing the same. The purpose is to provide.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an insulating film provided on a semiconductor substrate of one conductivity type; and a gate provided on the insulating film. An electrode, a first diffusion region of opposite conductivity type provided in the semiconductor substrate located on a side of the gate electrode,
A second diffusion of the opposite conductivity type provided near the surface of the first diffusion region;
Region and said gate via said first and second diffusion regions
A third diffusion region of the opposite conductivity type facing the electrode;
The second diffusion region is determined from the impurity concentration of the first diffusion region.
The impurity concentration of the second diffusion region is high and the impurity concentration of the second diffusion region is high.
The third diffusion region has an impurity concentration higher than a pure concentration .

A semiconductor device according to claim 2 of the present invention.
Method of forming an insulating film on a semiconductor substrate of one conductivity type
And forming a gate electrode on the insulating film
And inside the semiconductor substrate located on the side of the gate electrode.
Injection of opposite conductivity type ions with different acceleration energy at least twice
Forming a diffusion region by applying
Performing a part of ion implantation, wherein the diffusion region is
In the forming step, impurities on the surface of the diffusion layer region are formed.
It is characterized in that the concentration is higher than the bottom.
Further, a method of manufacturing a semiconductor device according to claim 3 of the present invention.
The method according to claim 2, wherein the diffusion region is formed two or more times.
The ion implanted species with different acceleration energy above is arsenic or
It is characterized by being phosphorus. Also, claim 4 of the present invention
The method of manufacturing a semiconductor device according to claim 2, wherein
Two or more different acceleration energies to form the diffusion region
Ion implantation is performed by rotating ion implantation or large tilt ion implantation.
It is characterized in that it is turned on . Claim 5 of the present invention
The method of manufacturing a semiconductor device according to claim 2, wherein
After forming the region, a side wall is formed on the side of the gate electrode.
A spacer, and then a part of the diffusion region
It is characterized by performing ion implantation. In addition, the contract of the present invention
The manufacturing method of a semiconductor device according to claim 6 is the method according to claim 2.
The impurity is boron and has different acceleration energies.
In addition, one of the acceleration energies is from 100 KeV to 200 KeV.
Range, other acceleration energy from 20 KeV to 100 KeV
It is characterized by being in the range. Claims of the present invention
The method of manufacturing a semiconductor device according to claim 7, wherein
The semiconductor substrate is N-type and the impurity concentration of the semiconductor substrate is 1
In particular, the range is from × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁶ cm ^-3.
Sign . Further, according to the semiconductor device of the present invention,
The manufacturing method according to claim 6, wherein 100 KeV to 200 KeV.
The injection amount at an acceleration energy in the range of V is 0.6 ×
It should be in the range of 10 ¹² cm ^-2 to 1.6 × 10 ¹² cm ^-2
Features. A semiconductor device according to claim 9 of the present invention.
The manufacturing method of claim 6, wherein 20 KeV to 100K
The injection amount at an acceleration energy in the range of eV is 0.2
× It from 10 ^{1 2} cm ^-2 in the range of 1.2 × 10 ¹² cm ^-2
It is characterized by.

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

According to the above structure, the diffusion region is formed by implanting the opposite conductivity type ions at two or more times with different acceleration energies into the semiconductor substrate located on the side of the gate electrode, thereby forming the impurity concentration of the medium concentration diffusion region. Can be increased near the surface of the semiconductor substrate and near the bottom of the high concentration diffusion region.
The second ion implantation of the acceleration energy makes it possible to locate the impurity distribution of the medium-concentration diffusion region at the PN junction of the high-concentration diffusion region and the semiconductor substrate 11, thereby defining the breakdown voltage of the semiconductor device. The impurity concentration distribution at the PN junction near the boundary between the region and the medium-concentration diffusion region becomes gentle, the electric field intensity is reduced, and the breakdown voltage of the semiconductor device is improved. In addition, the impurity concentration of the medium-concentration diffusion region on the surface of the semiconductor substrate is appropriately adjusted by ion implantation of acceleration energy after the second time, and the driving capability of the semiconductor device is improved by appropriately increasing the impurity concentration.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, a semiconductor substrate
Reference numeral 11 denotes N-type silicon, and an insulating film 12 formed on the semiconductor substrate 11 includes a silicon oxide film or the like.
The gate electrode 13 formed on the insulating film 12 is made of polysilicon. Also, the offset region 14 is a gate electrode
13 is a P-type medium-concentration diffusion region of the opposite conductivity type provided in the semiconductor substrate 11 located on one side of 13. Further, the drain 15 is connected to the gate electrode 13 through the offset region 14.
Of the opposite conductivity type provided in the semiconductor substrate 11 facing the
It is a high concentration diffusion region of the mold. Further, the source 16 is a P-type high-concentration diffusion region of the opposite conductivity type provided in the semiconductor substrate 11 located on the other side of the gate electrode 13. The high-concentration diffusion regions of the drain 15 and the source 16 face each other via the gate electrode 13 and the offset region 14. The impurity concentration of the offset region 14 which is a medium concentration diffusion region is set near the surface of the semiconductor substrate 11 and the drain concentration which is a high concentration diffusion region.
Construct a high concentration near the bottom of 15. Thus, the feature of the present invention resides in the impurity distribution of the offset region 14.

FIG. 2 is an impurity distribution diagram of the line segment GH and the line segment IJ shown in FIG. 1. Since the impurity distribution of the high-concentration diffusion region of the drain 15 and the source 16 is the same, the line segment IJ has been identified and the source The 16 side is selected. In FIG. 2, a characteristic P indicated by a solid line is an impurity distribution in a line segment GH in the offset region 14, a characteristic Q indicated by a dotted line is an impurity distribution in a line segment IJ in the source 16, and the impurity concentration is Medium concentration, high concentration in drain 15 and source 16. In order to improve the breakdown voltage, the breakdown voltage of the semiconductor device is defined.
The depletion layer at point K) extends widely in a parallel plate shape as much as possible,
The configuration is such that the electric field strength is reduced. For this purpose, the offset region 14 has a high impurity distribution located at the PN junction between the drain 15 and the semiconductor substrate 11.
As a result, the depth of the offset region 14 is deeper than the drain 15.

The semiconductor substrate 11 has an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm in order to realize a sufficiently high withstand voltage.
It is about ^-3 . If the impurity concentration is too low, drain 1
5. Punch-through occurs between sources 16. If the concentration is too high, the PN junction breakdown voltage between the drain 15 and the semiconductor substrate 11 decreases. Therefore, in this embodiment, the length of the gate electrode 13 is shortened to 2 to 3 μm as compared with the conventional example in order to achieve a small occupation area and a high driving capability corresponding to the fine processing technology. Therefore, in order to prevent punch-through, the impurity concentration is set slightly higher than in the conventional example.

Further, the depth of the drain 15 is about 0.3 μm. The impurity concentration is 1 × 10 ²⁰ cm ⁻³ or more.
Further, the depth of the offset region 14 is about 0.4 μm.
The impurity concentration is 5 × 10 ¹⁶ cm ^{−3 on the} surface of the semiconductor substrate 11.
At the position of the PN junction between the drain 15 and the semiconductor substrate 11, it is about 5 × 10 ¹⁶ cm ⁻³ .

Under these conditions, the length of the gate electrode 13 is 2
μm, the length of the offset region 14 is 3 μm, and the withstand voltage is about −
A semiconductor device having 70 V and a drain current of about −25 μA / μm is realized.

FIG. 3 is a sectional view showing each step of the method of manufacturing the semiconductor device of FIG. First, as shown in FIG. 3A, an insulating film 12 is formed on a semiconductor substrate 11 made of N-type silicon, and the thickness of the insulating film 12 is 30 nm to 50 nm.
m. This film thickness is set to an appropriate value in consideration of a desired threshold voltage, a voltage applied to the drain 15, and the like. Further, the gate electrode 13 has a thickness of 40 on the insulating film 12.
It is formed of polysilicon of about 0 nm.

Next, as shown in FIG.
The semiconductor substrate 11 located on the other side of the gate electrode 13
Cover the upper part and the gate electrode 13. Uses medium current ion implanter
The high acceleration energy is about 130 KeV and the dose is
6 × 10¹²cm^-2From 1.6 × 10 ¹²cm^-2Range of boron
(B⁺) Is ion-implanted.

Further, as shown in FIG. 3C, the low acceleration energy is reduced to about 50 Ke using a medium current ion implanter.
V, dose amount from 0.2 × 10 ¹² cm ^-2 to 1.2 × 10 ¹² cm ^-2
Similarly, boron (B ⁺ ) is subsequently ion-implanted within the range. In this manner, in the semiconductor substrate on one side of the gate electrode 13, ions of the opposite conductivity type are implanted twice or more with different acceleration energies to form an offset region 14 ′ as a diffusion region. Note that the two ion implantations shown in FIGS. 3B and 3C may be realized by a large tilt implantation, a rotation implantation, or the like.

Here, the surface of the semiconductor substrate 11 located on the other side of the gate electrode 13 is
When boron (B ⁺ ) is ion-implanted with high acceleration energy of about 130 KeV, boron (B ⁺ ) penetrates the gate electrode 13 and penetrates the channel region between the drain 15 and the source 16. This is to prevent them from doing so.
The thickness of the resist 17 is about 1 μm. Note that the resist 17 may not be used depending on the acceleration energy at the time of ion implantation and the material of the gate electrode 13. The heat treatment may be added as necessary to activate the ions, and a heat treatment at about 600 ° C. may be performed after the ion implantation shown in FIG. 3C.

Further, as shown in FIG.
17 is removed, and both sides of the insulating film 12 and the gate electrode 13 are T
A side wall spacer 18 is formed of an EOS insulating film or the like. Then, a part of the gate electrode 13 and the offset region 14 '
(Offset region 14) is covered with a resist 19. Further, BF ₂ is ion-implanted to form a drain 15 and a source 16.

Here, the driving capability and the withstand voltage have a trade-off relationship such that when the driving capability is improved, the withstanding voltage is reduced, and when the withstanding voltage is improved, the driving capability is reduced. For this reason, the first two ion implantation conditions are selected to best achieve these tradeoffs. That is, a high impurity energy distribution of the offset region 14 is positioned at the PN junction between the drain 15 and the semiconductor substrate 11 by ion implantation with a high acceleration energy of 130 KeV. As a result, the withstand voltage of the semiconductor device is regulated.
The breakdown voltage is improved by making the impurity concentration distribution of the PN junction near the boundary between the semiconductor substrate 11 and the semiconductor substrate 11 smooth, and the depletion layer here is extended as much as possible in a parallel plate shape so that the electric field strength is reduced. be able to. Next, by appropriately adjusting the impurity concentration of the offset region 14 on the surface of the semiconductor substrate 11 on the surface of the semiconductor substrate 11 by ion implantation at a low acceleration energy of 50 KeV, the impurity concentration near the semiconductor substrate surface of the offset region 14 is appropriately increased. Ability can be improved.

The upper limit of the high acceleration energy must be such that the impurity distribution implanted by the ions overlaps with the impurity distribution due to the low acceleration energy, and the surface of the semiconductor substrate 11 becomes a medium-concentration P-type diffusion region. . In addition, the lower limit is such that the impurity distribution obtained by ion implantation overlaps the impurity distribution due to low acceleration energy, and the drain 15 and the semiconductor substrate 11
Is required to have a gentle distribution shape near the PN junction. On the other hand, the magnitude of low acceleration energy is
Determined according to the high acceleration energy. That is, it is necessary to set the energy range so as to overlap with the impurity distribution due to the high acceleration energy and make the surface of the semiconductor substrate 11 a medium-concentration P-type diffusion region.

As a result of the experiment, the high acceleration energy was 100 Ke
A range from V to 200 KeV is appropriate. Accordingly, the low acceleration energy is suitably in the range of 20 KeV to 100 KeV.

FIG. 4 shows the dependence of the breakdown voltage on the length of the offset region 14 when the length of the gate electrode 13 is 3 μm.
As shown in FIG. 4, the breakdown voltage of the characteristic S of the present invention always indicated by a solid line is larger than the characteristic T of the conventional example indicated by a dotted line at all the lengths of the offset regions 14. In the characteristic S, a sufficient withstand voltage is obtained even when the length of the offset region 14 is reduced. Further, as the length of the offset region 14 decreases, the driving capability increases. Therefore, a semiconductor device with high driving capability and high withstand voltage can be realized.

As shown in the output circuit of FIG. 5 using the semiconductor device having a high driving capability and a high withstand voltage formed in this way, a transistor 21 is connected in series with a resistor 22, and a display tube such as a fluorescent display tube is used. Used to drive etc.

Therefore, by increasing the impurity concentration of the offset region 14 formed in the semiconductor substrate 11 located on the side of the gate electrode 13 near the surface of the semiconductor substrate 11, high driving capability can be obtained. By increasing the height near the bottom of the drain 15, a high breakdown voltage can be achieved. Further, by performing ion implantation at two or more times with different acceleration energies in the semiconductor substrate 11 located on the side of the gate electrode 13 to form a diffusion layer, it is possible to perform ion implantation only without using the conventional thermal diffusion. A semiconductor device with high driving capability and high withstand voltage can be realized, and characteristics of a transistor such as a logic circuit portion are not impaired.

In the present embodiment, the step of forming the sidewall spacer 18 on the side of the gate electrode 13 is performed after the step of ion implantation with low acceleration energy shown in FIG. The ion implantation may be performed between the step of performing ion implantation and the step of performing ion implantation with low acceleration energy. In this case, ion implantation with low acceleration energy is performed first, and then the sidewall spacer 18 is formed. . Thereafter, ion implantation with high acceleration energy is performed. This is to ensure that the offset region 14 below the sidewall spacer 18 becomes P-type on the surface of the semiconductor substrate 11. Further, in the present embodiment, the case where the offset region 14 is located on one side of the gate electrode 13 is shown, but it may be located on both sides of the gate electrode 13. Further, in this embodiment, a P-channel transistor is taken as an example,
The present invention is also effective for channel transistors. At that time, the same ion implantation of phosphorus or arsenic into the P-type semiconductor substrate is performed twice or more with different acceleration energies.

[0042]

As described above, according to the present invention, the impurity concentration of the medium-concentration diffusion region of the opposite conductivity type formed in the semiconductor substrate located on the side of the gate electrode is made higher than that of the vicinity of the surface of the semiconductor substrate. By configuring the semiconductor device high near the bottom of the region, a semiconductor device with high driving capability and high withstand voltage can be realized. In addition, the step of implanting opposite conductivity type ions at least twice in the semiconductor substrate located on the side of the gate electrode with different acceleration energies to form a diffusion region impairs the characteristics of the transistor in the logic circuit portion. Not
A method for manufacturing a semiconductor device having a high driving capability and a high withstand voltage in a small occupied area compatible with the fine processing technology can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is an impurity distribution diagram in a line segment GH and a line segment IJ shown in FIG.

FIG. 3 is a sectional view showing each step of a manufacturing method in the semiconductor device of FIG. 1;

4 is a diagram showing the dependence of the breakdown voltage on the length of the offset region 14 when the length of the gate electrode 13 in FIG. 1 is 3 μm.

FIG. 5 is an output circuit diagram using the semiconductor device of FIG. 1;

FIG. 6 is a sectional view of a conventional semiconductor device.

FIG. 7 is an impurity distribution diagram in a line segment AB and a line segment CD shown in FIG. 6;

8 is a sectional view showing each step of a manufacturing method in the semiconductor device of FIG. 6;

[Explanation of symbols]

 11 Semiconductor substrate 12 Insulating film 13 Gate electrode 14 Offset region 15 Drain 16 Source 18 Sidewall spacer 21 Transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (9)

(57) [Claims] An insulating film provided on a semiconductor substrate of one conductivity type; a gate electrode provided on the insulating film; and an opposite conductive type provided in the semiconductor substrate located on a side portion of the gate electrode. A first diffusion region; and a first diffusion region near a surface of the first diffusion region.
The provided second diffusion region of the opposite conductivity type, the first and second diffusion regions;
Reverse conductivity type facing the gate electrode through a diffusion region
And a third diffusion region of the first diffusion region.
The impurity concentration of the second diffusion region is higher than the impurity concentration;
And a semiconductor device in which the impurity concentration of the third diffusion region is higher than that of the second diffusion region. 2. An insulating film is formed on a semiconductor substrate of one conductivity type.
Forming a gate electrode on the insulating film
And inside the semiconductor substrate located on the side of the gate electrode.
Injection of opposite conductivity type ions with different acceleration energy at least twice
Forming a diffusion region by applying
Performing a part of ion implantation, wherein the diffusion region is
In the forming step, impurities on the surface of the diffusion layer region are formed.
Characterized in that the concentration is higher than the bottom
A method for manufacturing a conductor device . 3. The method according to claim 1, wherein the diffusion region is formed two or more times.
Arsenic or phosphorus is the ion implanted at the accelerating energy
3. A method of manufacturing a semiconductor device according to claim 2, wherein
Law. 4. The method according to claim 1, wherein said diffusion region is formed two or more times.
Acceleration energy ion implantation is performed by rotating ion implantation or
3. The method for manufacturing a semiconductor device according to claim 2 , wherein the ion implantation is a large gradient ion implantation . 5. The method according to claim 1 , further comprising the step of forming the gate electrode after forming the diffusion region.
A sidewall spacer is formed on the side, and then the
Ion implantation for a part of the diffusion region.
The method for manufacturing a semiconductor device according to claim 2 . 6. The method according to claim 1 , wherein the impurity is boron,
Energy from 100 KeV to 200
KeV range, the other acceleration energy from 20 KeV to 10
3. The method for manufacturing a semiconductor device according to claim 2, wherein the range is 0 KeV . 7. The semiconductor substrate is of an N type, and the semiconductor substrate has
Net objects concentration from 1 × 10 ¹⁵ cm ^-3 in the range of 1 × 10 ¹⁶ cm ^-3
3. A method for manufacturing a semiconductor device according to claim 2 . 8. An acceleration energy in the range of 100 KeV to 200 KeV.
The injection amount to be implanted with lug is from 0.6 × 10 ¹² cm ^-2 .
7. The method for manufacturing a semiconductor device according to claim 6, wherein the range is 6 × 10 ¹² cm ⁻² . 9. An acceleration energy in a range of 20 KeV to 100 KeV.
The injection amount to be implanted with the energy is from 0.2 × 10 ¹² cm ⁻² .
7. The method for manufacturing a semiconductor device according to claim 6, wherein the range is 2 × 10 ¹² cm ⁻² .