JPS5854711A - Differential amplifier - Google Patents

Abstract

PURPOSE:To improve an input offset voltage and its temperature drift characteristics, by using weighted junction field effect transistors (JFET) and a Zener sapping technique. CONSTITUTION:An input offset voltage correction circuit consists of J5-J8 being JFETs and Zener diodes Z1-Z4, and the gate region of the J5-J8 is used in common and the gate is connected to a power supply terminal. The saturation current IDSS of the J5-J8 is weighted and the ratio of the IDSS is taken as IDSSJ5:IDSSJ6:IDSSJ7:IDSSJ8=1:2:4:8. A differential amplifier consists of J1-J4 being JFETs. A Zener diode for sapping is connected between the source and drain of the J5-J7. The drain of the J5-J7 is connected in common to the drain of the J1 and the drain of the J8 is connected to the drain of the J2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential amplifier, and more particularly to a method for compensating its input offset voltage.

Commonly known as J: In semiconductor integrated circuits such as operational amplifiers and comparators whose input stage is composed of differential amplification, internal element mismatching and conversion from differential to single-ended Input offset voltage occurs due to circuit mismatch, etc. Ideally, this input offset voltage should be oV. Therefore, in high-precision operational amplifiers, comparators, etc.

Insert a resistor at the point where the offset voltage Is is adjusted, and perform laser trimming,
The input offset voltage is adjusted to be as small as possible using techniques such as zener wrapping] and rimming.

FIG. 1 shows a conventional 11-mi input power supply positive circuit using the Zener wrapping technique and its differential input stage. In FIG. 1, the gates of Jl and J2, which are P-channel junction field effect transistors (hereinafter referred to as u J I", Ia'L'), are differential input terminals, and the sources are mutually connected. J3.J, which is the same P-channel JPET, is connected to the current source I.
4 act as active loads for Jl and J2, respectively, with their gates and sources interconnected and connected to the drains of Jl and J2, respectively.

Also, at this connection point, the JFF of the input offset compensation circuit is connected.
The drains of 1T J5 r J6 are connected to each other, and both gates are connected to a power supply terminal. The sources are each connected to the power supply terminals via a trimmed resistor "1 + R2. The resistors "1 r "2 are each connected to the J
5. This is a resistor that controls the drain current of J6, and is trimmed so that the input offset voltage approaches 0. Here, the drain currents ID5 and ID6 of J5 and J6 are respectively... (1) Also, Jl and J2. The input offset voltage (Vos) regarding the mismatching of J3 and J4 vp and ID88 is VO
8=VG8(Jl) -VO2(J2) then J5 +
J6 + ``1 #If the input ONCERA 11 pressure when inserting R2 is ■.,', 3- Therefore, by adjusting ID5 and ID6, that is, by trimming R1°R2, Vos can be brought closer to OV. .

However, the first drawback of the circuit shown in Fig. 1 is that the offset correction circuit (s indicated within the broken line in Fig. 1) is
Mismatch between ID5 and ID6 before trimming (circuit consisting of J5 * J6 * "1 m" 2),
i.e. Th ID88 (J5) and ID88 (J6)
% Due to the mismatch between R1 and L1'2, there was a drawback that the initial offset voltage (offset voltage before trimming) was worse than when this offset voltage correction circuit was not provided.

A second drawback is that this offset correction circuit has an adverse effect on the temperature drift of the input offset voltage. This means that the temperature coefficient of the diffused resistor and JFET ID8B built into the monolith is several thousand ppm.
/C is also important, and this is the cause of worsening the temperature drift of the input voltage. Furthermore, the variation in the absolute values of ID88 and the diffused resistance of %JPET is generally large, and since these vary independently, there is also a third drawback that the input offset voltage adjustment range also varies greatly.

The present invention aims to solve the above three drawbacks,
It is an object of the present invention to provide a semiconductor integrated circuit that can accurately adjust an input offset voltage regardless of variations in each parameter (ID88 and vp).

The differential amplifier of the present invention is a semiconductor integrated circuit comprising an amplifier having a differential pair field effect transistor at its input and an input offset voltage correction circuit, wherein the input offset voltage correction circuit has at least two or more correction circuits. Consisting of a field effect transistor and a switching element connected between the source and gate of the correction field effect transistor,
The drains of the differential pair field effect transistor and the correction field effect transistor are each connected in parallel.

The saturation current ID88 of the correction area effect transistor
The present invention is characterized in that each of the switching elements is weighted, and the switching elements are selectively short-circuited so that the input offset voltage of the amplifier is reduced.

Next, the present invention will be explained in detail using the drawings.

FIG. 2 is a circuit connection diagram showing one embodiment of the present invention. Note that the same parts as in FIG. 1 are given the same reference numerals and their explanations will be omitted.

Referring to FIG. 2, the input offset voltage correction circuit is as follows:
JI (1ET'') consists of J5 to J8 and Zener diodes Z1 to Z4, the gate regions of J5 to J8 are common, and the gate electrodes are connected to the power supply terminal. Here, ID58 of J5.-J8 is weighted.

The ratio of each ID88 is ID5S (J5): ID8S (J6): ID8
S (J7): ID88 (J8) = 1:2:4:8・
・・・・・・・・・・・・(5) The differential amplifier is composed of J1 to J4 as in FIG. Between the source and drain of J5 to J7.

Connect a Zener diode for Zaraping to each.

The drains of J5 to J7 are connected in common, the drain of J1 is connected to the drain of J8, and the drain of J8 is connected to the drain of J2. JF including Zenerwo that does not perform Zaraping here
When the ETil is pinched off, the drain current does not flow, and the Zener diode is placed in the return path, the saturation current ID5
8 is gone. These J5 to J8 are weighted as described above, so the sum of the drain currents of J5 to J8 is II, the drain current of J8 is IT, and the saturation current of J5 is In5s. , −(a02°+8
12"+a222) ID88 -----(6)IR-
It can be expressed as a32 ID58---[7). Here, ao to a3 correspond to the states of the Zaraping Zener diodes, and 1. It is assumed that the value is O in the non-short circuit state. Here, input offset voltage (Vn
s''') is tl-3?

Tonacie R* IIJ” 'D88)
The term 9- in the equation simply becomes the ratio of ID88. In integrated circuits.

Within the same chip, the relative temperature coefficients of DSB and V are well matched.Therefore, the degradation of the temperature characteristics of the input offset m due to the insertion of this offset correction circuit is smaller than that of the conventional one. In this way, by selectively shorting the Zener diodes in the circuit shown in the example, it is possible to drive the initial offset to 0, whether positive or negative.Also, in the state before trimming, J5 to J8 are all pinch-on.

Since the initial input offset voltage does not include the matching factor of J5 to J8, the initial input offset voltage can be expected to be better than that of the conventional example.

In addition, as another example, J3 and J4 in FIG.
By replacing the active load with an N-type transistor and configuring the constant current source I with the same P-channel type J1i'ET, the same effect as described above can be achieved.

As explained above, according to the present invention, the weighted J
By using PET and Zener wrapping technology, it is possible to provide an amplifier with excellent input off-voltage and temperature drift characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a conventional circuit in which offset voltage is adjusted by resistor trimming, and FIG. 2 is a circuit configuration diagram showing an embodiment of a differential amplifier including an input offset correction circuit according to the present invention. J1~J8...P channel junction type 1i'ET
, Z1~24, , Zener diode, 1
1. l, l' are also 2...resistance. ■・・・Constant current source, 1・・・DC power supply terminal,
2... Ground terminal, 3, 4... Difference Mrb
Input terminal.゛. −10=

Claims (1)

[Claims] an amplifier with a differential pair field effect transistor at the input;
In a semiconductor integrated circuit comprising a manual offset voltage correction circuit, the input offset voltage correction circuit includes at least two correction field effect transistors and a switching element connected between the source and gate of the correction field effect transistor. The differential pair field effect I transistor and the drain of the correction field effect transistor are connected in common, and each of the saturation currents 17If of the correction field effect transistor is weighted, A differential amplifier characterized in that the switching element is selectively short-circuited so that an input offset voltage of the amplifier is reduced.