JPS6292505A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To reduce the temperature dependency of an offset voltage by matching the area ratio of emitters of transistors (TR) so as to eliminate the offset voltage. CONSTITUTION:PNP TRs Q5, Q6 as loads are connected to PNP TRs Q1, Q2 of a differential input section to which a constant bias current is fed from a constant current circuit CC to form a mirror circuit. The TRs Q5, Q6 are formed as multi-emitter TRs whose emitter areas S1-S4 differ, and in selecting emitters so as to match the emitter areas A5, A6 of the TRs Q5, Q6 as A5/A6=1, the offset voltage V'OFF based on equation I is 0 independently of the temperature. As a result, the temperature dependency of the offset voltage is reduced. In equation, VT is a thermal voltage of the TRs Q1, Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit with improved temperature dependence of its offset voltage.

<Prior Art> FIG. 4 shows the configuration of a conventional differential amplifier circuit. Positive power terminal +
One end of a constant current circuit CC is connected to V.

The other end is a PNP type transistor Q1. Each is connected to the emitter of Q2.

NPN type transistors Q3 . The collector of Q4 is connected, the emitter of transistor Q3 is connected to the negative power supply terminal
The emitters of 4 are each connected to the negative power supply terminal -V via a resistor B1.

Collector and pace of transistor Q3, transistor Q
3. Each pace in Q4 is interconnected.

Transistors Q3 and Q4 function as a mirror circuit, and transistors Q1. It forms the active load in Q2.

Each pace of transistors Q1 and Q2 has an input voltage V,
, V, -'' are input, respectively, and the transistor Q
From the collector of 4, the difference voltage of the input voltage (V, -v;)
K corresponding output current I. ul is obtained.

In the above configuration, if the input offset voltage voFF is set to vbel and the voltage between the base and emitter of each transistor Q1'Q2 is set to vbel''be2, the following equation is obtained.

. FF bel be2”
Here, transistor Q1. The collector current flowing in each collector of Q2 is Icl' Ic2, and the reverse saturation current and thermal voltage are I3 and VT (=kT/q, k:
Boltzmann's constant, T: Ja/Xilan temperature, q: electron charge), then the following is true. On the other hand, the collector current Icl・"c2 of each transistor Q11Q2 is the voltage between the base of the transistor Q3.A4 and the negative power supply -V. If the voltage between them is Vn, then B 1c1 #J, A3exp -'31T. However, J is the current density, and A3+A4 is the emitter area of the transistors Q3 and Q4.

Using equations (2) to (4), the input offset voltage v
OFF is.

In this case, if the emitter area ^3 of the transistor Q3 is smaller than the emitter area A4 of the transistor Q4 due to the W3 ratio, the offset voltage is negative.
The resistor R1 is il[ and the offset voltage V as a whole. 1
．． can be set to zero.

Eyatsuta area A3. If A4 is opposite to the above, by inserting a resistor into the emitter of transistor Q3, offset voltage ■ is generated as above. F can be made zero.

Transistor Q3. If a resistor is inserted into both emitters of A4 so that both can be adjusted, the offset voltage will be - regardless of the emitter area ratio A3/A4.

F can be made zero.

<Problems to be Solved by the Invention> By the way, since the resistor R1 is formed in a semiconductor process, its temperature coefficient is approximately +2000 PPM/°C, and the collector current is low. 2. In other words, the temperature coefficient of the bias current I of the constant current circuit CC is generally +2000 PPM.
/°C. Therefore, in total, O ~ + 400
It has a temperature coefficient of the order of 0 PPM/tl. Also,
Since the thermal voltage VT also has a temperature coefficient of about +3300 PPM/°C, there is a drawback that even if the offset voltage vOFF is set to zero by the resistor R1, the output fluctuates considerably depending on the temperature.

〈Means for solving problems〉 This invention aims to solve the above problems.

A constant current source that supplies a constant bias current, a differential input section in which a bias current is supplied by emitter-coupling a pair of input transistors, and a load transistor in which at least one of the input transistors is a multi-emitter load. It is equipped with a mirror circuit that takes out an output signal from this collector, and a lead wire that is disconnectably connected between the multi-emitters, and by selecting the cutting point of this lead wire, the emitter area of the load transistor can be reduced. This is a configuration that can be selected.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

Incidentally, parts having the same functions as those in the prior art are designated by the same reference numerals, and explanations thereof will be omitted as appropriate.

Figure Wc1 is a circuit diagram showing an embodiment of the present invention.

A5. A6 is an NPN type transistor, and transistors Q1. Connected as the active load of Q2.

Forms a mirror circuit. Transistor Q5. The emitter of Q6 is a multi-emitter, and the area S of each emitter is Sl:S2:S3:S4:~=1:2
:4:8:～ is selected.

Furthermore, each emitter of the transistor Q6 is connected to an aluminum wiring t1.
．． 12. t3. Connected at t4~.

Input offset voltage in this case ■. FF sets the voltage between the base and emitter of transistors Q and Q to VV.
Then, we get the following formula.

beIIbe2 Each transistor Q1. If the flow is Z I/, then c
It becomes l c2. Transistor Q5. If the voltage between the base and emitter of Q6 is 4, then transistor Q1. Collector current of Q2 ■. '1 r Ic2 is the transistor Q5
．． The emitter area of Q6 is A5. As A6, it becomes. Offset voltage V from equations (7) to (9). 1.
is dependent on the area ratio A5/A6 of the emitters of transistors Q51Q6.

Therefore, transistor Q5. Q6 emitter area ratio A
Offset voltage v caused by the deviation of s/A 6
OFF can be set to tnA5/A6=0 by cutting the Al ξ wirings 11, 12~ with a laser or the like so that the area ratio A5/A6 becomes 1, so that it is not affected by temperature.

Figure yg2 is a circuit diagram showing another embodiment of the present invention.

Transistors QQ forming the differential input section shown in Figure 1
It has a two-stage configuration in which the emitter current of the transistor Q7゜1' 2 Q8 flows through the base of the transistor Q7゜1' 2 Q8.

FIG. 3 is a circuit diagram showing a $1.3 embodiment of the present invention. The base and emitter of transistor Q9 are connected between the collector and base of transistor Q5, and the collector is connected to the positive power supply terminal +VK, making it a current mirror circuit that is not affected by current amplification factor or B. . The output voltage is from the collector of transistor Q6 to transistor Q
It is taken out from the collector of transistor Qll via IO' Qll.

Furthermore, in the circuit shown in FIG.
The object of the present invention can also be achieved with a configuration in which C is set to thin 7.

Furthermore, the object of the present invention can be similarly achieved by using a configuration in which a voltage amplifying circuit or the like is added to the output end of the circuit shown in FIG. 1.

In the circuit of FIG. 1, the area of the emitter of the transistor Q6 is changed, but the area of the emitter of the transistor Q5 may be changed.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, the offset voltage is removed by using a configuration that matches the area ratio of the emitter of the transistor. Temperature dependence and bias current I. The impact of this can be significantly reduced.

[Brief explanation of drawings]

FIG. 2 is a circuit diagram showing the configuration of an embodiment of the present invention shown in FIG. 1; FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention, FIG. 3 is a circuit diagram showing the configuration of a third embodiment of the present invention, and FIG.
The figure is a circuit diagram showing the configuration of a conventional differential amplifier circuit. v, ■...Input voltage, Q1-Qll...Transistor, SCC...Constant current circuit, ■. ...bias current, t1
~t4...Lead wiring.

Claims (1)

[Claims] a constant current source that supplies a constant bias current; a differential input section that emitter-couples a pair of input transistors to which the bias current is supplied; and at least one of the input transistors is a multi-emitter load. A mirror circuit that has a load transistor and takes out an output signal from the collector thereof, and a lead wire in which the multi-emitters are connected in a disconnectable manner, and the load transistor can be connected by selecting a cutting point of the lead wire. A differential amplifier circuit characterized by selecting an emitter area of.