JPH0153931B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a differential amplifier capable of reducing offset voltage.

[Prior art]

FIG. 1 shows a conventional differential amplifier. In the figure, 1 and 2 are input terminals, and 3 and 4 are differential input circuits 2 and 4.
The commonly connected emitters of the transistors 3 and 4 are connected to the first bias current source 5, and the transistors 3 and
Each of the bases of 4 is connected to the input terminals 1 and 2.

6 and 7 are transistors forming a constant current circuit 22, and a diode terminal connecting the collector and base of one transistor 6 of the constant current circuit 22 is connected to the collector of one transistor 3 of the differential input circuit 21. The collector terminal of the other transistor 7 of the constant current circuit 22 is connected to the collector of the other transistor 4 of the differential input circuit 21.

8 is an output buffer transistor, the base of which is connected to the collector terminal of the transistor 7 of the constant current circuit 22, the emitter of which is connected to the second bias current source 9, and the collector of which is connected to the ground. . Further, 10 is an output terminal taken out from the connection point between the second bias current source 9 and the output buffer transistor 8, and 11 is a power supply.

Next, the operation of this conventional differential amplifier will be explained.

When using this conventional differential amplifier as a negative feedback amplifier, assuming that the voltage amplification degree is sufficiently high (gmRL10 ^{3 to 4} ), when the constant current circuit 22 is configured, the collector currents I6 and I7 flowing through the transistors 6 and 7 The circuit is balanced when the following equations (1) to (4) become equal: I11+I12=I10 ……(1) I7=I12+I12/hfep8 ……(2) I6=I11 ……(3) I6=I17 ...(4) holds, and from this, the following formulas (5) to (7) I11=1/2 (I10+I2/hfep8) ...(5) I12=1/2 (I10−I2/hfep8) ...(6) I10=I1(1-2/hfep3) ...(7) holds true. Here, hfep3 is the current amplification factor of transistor 3, and hfep8 is the current amplification factor of transistor 8.

From the above equations (5) to (7), the offset voltage ΔV when this circuit is at the equilibrium point in the active region is expressed by the following equation (8).

ΔV=kT/qlnI11/I8−kT/qlnI12/I8=k
T/qlnI11/I12=kT/qln[1+(1/hfep8)・(I2
/I10)/1-(1/hfep8)・(I2/I10)]...(8) In the above equations (7) and (8), hfep3≒10, I1=
If 10μA, hfep8=20, I2=100μA, ΔV is 30
(mV).

When the offset voltage increases in a differential amplifier, problems such as increased errors occur. In conventional differential amplifiers, to reduce the offset voltage to prevent this error from increasing, it is necessary to lower I2 from 100 μA to, for example, 10 μA at the expense of increasing the output impedance. There were some shortcomings.

[Summary of the invention]

The present invention was made to eliminate the above-mentioned conventional drawbacks, and includes a correction transistor having the same shape and size as the output buffer transistor, a base of the correction transistor, and the output buffer transistor. To provide a differential amplifier capable of reducing offset voltage without increasing output impedance by providing a second constant current circuit inserted between the base of the transistor and improving accuracy as a result. It is an object.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 1 indicate the same or equivalent parts, and 12 is a correction PNP transistor, which is the output buffer transistor 8
The correction transistor 12 is inserted and connected between the third bias current source 13 and the ground.

6 and 7 are NPNs forming the first constant current circuit 22
14 and 15 constitute a second constant current circuit 23 which is a current mirror circuit.
It is an NPN transistor. The second constant current circuit 2
A diode terminal connecting the collector and base of one transistor 15 of No. 3 is connected to the base of the correction transistor 12, and the second
The collector terminal of the other transistor 14 of the constant current circuit 23 is connected to the base of the output buffer transistor 8.

Next, the operation will be explained.

In FIG. 2, the base current IB12 of the correction transistor 12 is expressed by the following formula (9) IB12=I3/hfep12 (9), and the transistor 14, which constitutes the second constant current circuit 23 which is a current mirror circuit, Since the emitter areas of transistors 15 and 15 are equal to each other, transistor 14
The collector current I14 of the output buffer transistor 8 is expressed by the following equation (10): I14≒IB12 (10), and the effective input current I8' of the output buffer transistor 8 is expressed by the following equation (11): I8'=I2/hfep8−I14=I2 /hfep8−I3/hfep12
...(10) becomes. Here, hfep12 is the current amplification factor of the transistor 12. In addition, the above equation (10) corresponds to I2/hfep8 in the above equation (8), and the equation (10) is converted into (8).
Substituting into the equation (12) below, ΔV=kT/qln[1+(1/I10)・(I2/
hfep8−I3/hfep12)/1−(1/I10)・(I2/hfep8
−I3/hfep12)]...(12). Here, the second and third bias current sources 9, 1
3 is set to I2=I3, and transistors 8 and 12 have the same shape and size, so the current amplification factor of transistors 8 and 12 is
It can be set as hfep8≒hfep12.

In this way, the bias current can be set as I2 = I3, and the current amplification factor can be ideally compensated as hfep8 = hfep12, so
The offset voltage ΔV can be set to 0 (mV), and the output impedance can be lowered.

When the differential amplifier of this embodiment is used as a negative feedback amplifier (operational amplifier), it can be used in a wide range of consumer and industrial fields as a general-purpose operational amplifier.

Further, when the circuit of the present invention is constructed from a semiconductor integrated circuit, if the transistors 8 and 12 have the same shape and size and are placed adjacent to each other within the IC chip, the current amplification factor of the transistors 8 and 12 is
The characteristics of hfep8 and hfep12 are also well matched, and the correction effect becomes even greater.

In the above embodiment, the transistors 3 and 4 of the differential input circuit 21 and the output buffer transistor 8
and the correction transistor 12 is of PNP type,
These may be of NPN type.

〔Effect of the invention〕

As described above, according to the differential amplifier of the present invention, the base current of the output buffer transistor in the load stage of the differential amplifier circuit is corrected by the base current of the correction transistor having the same shape and size as the transistor. This has the effect of providing low output impedance and high accuracy (low offset).

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional differential amplifier, and FIG. 2 is a circuit diagram of a differential amplifier according to an embodiment of the present invention. 1, 2... Differential input, 5... First bias current source, 8... Output buffer transistor, 9... Second bias current source, 10... Output terminal, 12...
Correction transistor, 13... Third bias current source, 21... Differential input circuit, 22... First constant current circuit, 23... Second constant current circuit. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Two PNPs (or NPNs) whose emitter (or collector) common connection point is connected to the first bias current source and whose bases are connected to two differential inputs, respectively.
A differential input circuit consisting of transistors and a diode terminal connecting the collector and base of one of the NPN transistors are connected to one collector (or emitter) of the differential input circuit, and the other is connected to the diode terminal.
a first constant current circuit in which the collector terminal of the NPN transistor is connected to the other collector (or emitter) of the differential input circuit; ) is a second bias current source, an output buffer PNP (or NPN) transistor whose collector (or emitter) is connected to ground, and a third bias current source having the same shape and size as the output buffer transistor. a correction PNP (or NPN) transistor connected between the source and ground;
a second constant current circuit in which a diode terminal connecting the collector and base of one of the NPN transistors is connected to the base of the correction transistor, and a collector of the other NPN transistor is connected to the base of the output buffer transistor; , and an output terminal taken out from a connection point between the second bias current source and the output buffer transistor.