JPH0626223B2 - マイクロエレクトロニツクス半導体回路および積層回路を封止するための方法 - Google Patents

マイクロエレクトロニツクス半導体回路および積層回路を封止するための方法

Info

Publication number
JPH0626223B2
JPH0626223B2 JP60505156A JP50515685A JPH0626223B2 JP H0626223 B2 JPH0626223 B2 JP H0626223B2 JP 60505156 A JP60505156 A JP 60505156A JP 50515685 A JP50515685 A JP 50515685A JP H0626223 B2 JPH0626223 B2 JP H0626223B2
Authority
JP
Japan
Prior art keywords
layer
foil
microelectronic
synthetic material
sealable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60505156A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62500900A (ja
Inventor
メーレル・ウエルネル
グラフ・フオン・リユ‐テイツヒアウ・ハラルト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
METSUSAASHUMITSUTO BERUKO BUROOMU GmbH
Original Assignee
METSUSAASHUMITSUTO BERUKO BUROOMU GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by METSUSAASHUMITSUTO BERUKO BUROOMU GmbH filed Critical METSUSAASHUMITSUTO BERUKO BUROOMU GmbH
Publication of JPS62500900A publication Critical patent/JPS62500900A/ja
Publication of JPH0626223B2 publication Critical patent/JPH0626223B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
JP60505156A 1984-11-17 1985-11-18 マイクロエレクトロニツクス半導体回路および積層回路を封止するための方法 Expired - Lifetime JPH0626223B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE3442131.9 1984-11-17
DE19843442131 DE3442131A1 (de) 1984-11-17 1984-11-17 Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen
PCT/DE1985/000475 WO1986003055A1 (en) 1984-11-17 1985-11-18 Process for encapsulating micro-electronic semi-conductor and layer-type circuits

Publications (2)

Publication Number Publication Date
JPS62500900A JPS62500900A (ja) 1987-04-09
JPH0626223B2 true JPH0626223B2 (ja) 1994-04-06

Family

ID=6250592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60505156A Expired - Lifetime JPH0626223B2 (ja) 1984-11-17 1985-11-18 マイクロエレクトロニツクス半導体回路および積層回路を封止するための方法

Country Status (5)

Country Link
US (1) US4784872A (enExample)
EP (1) EP0202279B1 (enExample)
JP (1) JPH0626223B2 (enExample)
DE (1) DE3442131A1 (enExample)
WO (1) WO1986003055A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11914293B2 (en) 2017-01-31 2024-02-27 Flint Group Germany Gmbh Radiatioin-curable mixture containing low-functionalised, partially saponified polyvinyl acetate

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
JP2585006B2 (ja) * 1987-07-22 1997-02-26 東レ・ダウコーニング・シリコーン株式会社 樹脂封止型半導体装置およびその製造方法
DE3725269A1 (de) * 1987-07-30 1989-02-09 Messerschmitt Boelkow Blohm Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen
US4903118A (en) * 1988-03-30 1990-02-20 Director General, Agency Of Industrial Science And Technology Semiconductor device including a resilient bonding resin
EP0361194A3 (de) * 1988-09-30 1991-06-12 Siemens Aktiengesellschaft Verfahren zum Umhüllen von elektrischen oder elektronischen Bauelementen oder Baugruppen und Umhüllung für elektrische oder elektronische Bauelemente oder Baugruppen
US5219795A (en) * 1989-02-07 1993-06-15 Fujitsu Limited Dual in-line packaging and method of producing the same
JPH0322543A (ja) * 1989-06-05 1991-01-30 Siemens Ag 電子デバイスの被覆方法及び装置
JPH0521655A (ja) * 1990-11-28 1993-01-29 Mitsubishi Electric Corp 半導体装置および半導体装置用パツケージ
US4996170A (en) * 1990-07-30 1991-02-26 Motorola, Inc. Molding process for encapsulating semiconductor devices using a thixotropic compound
DE4027478A1 (de) * 1990-08-30 1992-03-05 Robert Dipl Ing Michaelides Schaltungsaufbau und herstellungsverfahren
DE4101042C1 (en) * 1991-01-16 1992-02-20 Messerschmitt-Boelkow-Blohm Gmbh, 8012 Ottobrunn, De Contact and encapsulation of micro-circuits using solder laser - and laser transparent contact film segments with conductor sheets of solderable material, geometrically associated with solder protuberances
US5271953A (en) * 1991-02-25 1993-12-21 Delco Electronics Corporation System for performing work on workpieces
US5240746A (en) * 1991-02-25 1993-08-31 Delco Electronics Corporation System for performing related operations on workpieces
US5368899A (en) * 1992-02-28 1994-11-29 Delco Electronics Corp. Automatic vertical dip coater with simultaneous ultraviolet cure
US5249101A (en) * 1992-07-06 1993-09-28 International Business Machines Corporation Chip carrier with protective coating for circuitized surface
US5390082A (en) * 1992-07-06 1995-02-14 International Business Machines, Corp. Chip carrier with protective coating for circuitized surface
EP0620591A1 (en) * 1993-04-12 1994-10-19 Delco Electronics Corporation Silicone over-mould of a flip-chip device
JP3258764B2 (ja) * 1993-06-01 2002-02-18 三菱電機株式会社 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法
SG68542A1 (en) * 1993-06-04 1999-11-16 Seiko Epson Corp Semiconductor device and manufacturing method thereof
US7084656B1 (en) 1993-11-16 2006-08-01 Formfactor, Inc. Probe for semiconductor devices
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
US7073254B2 (en) 1993-11-16 2006-07-11 Formfactor, Inc. Method for mounting a plurality of spring contact elements
US5820014A (en) 1993-11-16 1998-10-13 Form Factor, Inc. Solder preforms
US7200930B2 (en) 1994-11-15 2007-04-10 Formfactor, Inc. Probe for semiconductor devices
GB2295722B (en) * 1994-11-30 1997-12-17 Motorola Ltd Method of packaging integrated circuits
JPH09155918A (ja) * 1995-12-07 1997-06-17 Matsushita Electric Ind Co Ltd 樹脂封止電子製品の製造方法
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
DE69718693T2 (de) * 1996-03-08 2003-11-27 Matsushita Electric Industrial Co., Ltd. Elektronisches Bauteil und Herstellungsverfahren
DE19736090B4 (de) * 1997-08-20 2005-04-14 Daimlerchrysler Ag Bauelement mit Schutzschicht und Verfahren zur Herstellung einer Schutzschicht für ein Bauelement
US6138349A (en) 1997-12-18 2000-10-31 Vlt Corporation Protective coating for an electronic device
US5987358A (en) * 1998-02-17 1999-11-16 Intermedics, Inc. Semiconductor device packaging and method of fabrication
US6194290B1 (en) * 1998-03-09 2001-02-27 Intersil Corporation Methods for making semiconductor devices by low temperature direct bonding
JP2000219234A (ja) * 1999-01-29 2000-08-08 Bridgestone Sports Co Ltd ゴルフボール用箱
US6187613B1 (en) * 1999-11-04 2001-02-13 Industrial Technology Research Institute Process for underfill encapsulating flip chip driven by pressure
US6589802B1 (en) * 1999-12-24 2003-07-08 Hitachi, Ltd. Packaging structure and method of packaging electronic parts
DE10049288B4 (de) 2000-10-04 2004-07-15 Infineon Technologies Ag Elektronische Bauteile und eine Folienband zum Verpacken von Bonddrahtverbindungen elektronischer Bauteile sowie deren Herstellungsverfahren
FR2819935B1 (fr) * 2001-01-19 2003-04-25 Ela Medical Sa Procede de fabrication de circuits electroniques hybrides pour dispositifs medicaux implantables actifs
US6444501B1 (en) * 2001-06-12 2002-09-03 Micron Technology, Inc. Two stage transfer molding method to encapsulate MMC module
US20060182952A1 (en) * 2002-01-08 2006-08-17 Justo Roger J Encapsulated thermally conductive electrically insulating assembly and method to prepare same
DE10216652A1 (de) * 2002-04-15 2003-10-23 Orga Kartensysteme Gmbh Spritzgussverfahren zur Herstellung einer Chipkarte und nach diesem Verfahren hergestellte Chipkarte
DE10303449B4 (de) * 2003-01-29 2007-04-26 Siemens Ag Verfahren zum Umhüllen eines elektronischen Bauelementes
EP2596948B1 (en) * 2003-03-10 2020-02-26 Toyoda Gosei Co., Ltd. Method of making a semiconductor device
DE102004049955B4 (de) * 2004-10-13 2008-12-04 Schott Ag Verfahren zur Herstellung eines optischen Bauelements, insbesondere einer OLED
US7523546B2 (en) * 2005-05-04 2009-04-28 Nokia Corporation Method for manufacturing a composite layer for an electronic device
US20080087323A1 (en) * 2005-05-09 2008-04-17 Kenji Araki Concentrator Solar Photovoltaic Power Generating Apparatus
DE102005041100A1 (de) * 2005-08-30 2007-03-08 Siemens Ag Halbleiterstruktur mit einem lateral funktionalen Aufbau
DE102006012615A1 (de) * 2006-03-20 2007-10-11 Kromberg & Schubert Gmbh & Co. Kg Umhülltes Bauelement und Verfahren zu dessen Herstellung
US8051557B2 (en) * 2006-03-31 2011-11-08 Princo Corp. Substrate with multi-layer interconnection structure and method of manufacturing the same
DE102007035181B4 (de) * 2007-07-27 2011-11-10 Epcos Ag Verfahren zur Herstellung eines Moduls und Modul
US8957509B2 (en) * 2011-06-23 2015-02-17 Stats Chippac Ltd. Integrated circuit packaging system with thermal emission and method of manufacture thereof
JP2013055150A (ja) * 2011-09-01 2013-03-21 Toshiba Corp 半導体装置及びその製造方法
DE202012008242U1 (de) 2012-02-26 2012-11-09 Kromberg & Schubert Kg Verbindung eines ersten metallischen Bauteils mit einemumhüllten zweiten metallischen Bauteil
WO2018177500A1 (de) 2017-03-27 2018-10-04 Flint Group Germany Gmbh Verfahren zur herstellung von bildhaften reliefstrukturen
CN108401367B (zh) * 2018-02-26 2020-08-14 广州致远电子有限公司 塑封电子模块及其制作方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3608029A (en) * 1969-03-12 1971-09-21 Vitramon Inc Process for encapsulating electronic components
CH560999A5 (enExample) * 1973-08-16 1975-04-15 Bbc Brown Boveri & Cie
US3876461A (en) * 1973-09-04 1975-04-08 Motorola Inc Semiconductor process
GB1528203A (en) * 1974-10-18 1978-10-11 Matsushita Electric Industrial Co Ltd Epoxy composition for encasing semi-conductor devices
JPS5171792A (enExample) * 1974-12-19 1976-06-21 Minolta Camera Kk
DE2551778A1 (de) * 1975-11-18 1977-05-26 Siemens Ag Feuchtedicht umhuelltes elektrisches bauelement
US4048356A (en) * 1975-12-15 1977-09-13 International Business Machines Corporation Hermetic topsealant coating and process for its formation
DE2628823C3 (de) * 1976-06-26 1979-03-01 Standard Elektrik Lorenz Ag, 7000 Stuttgart Glaskeramischer Werkstoff zur Verkapselung von Halbleiterbauelementen
FR2404992A1 (fr) * 1977-10-03 1979-04-27 Cii Honeywell Bull Circuits electriques integres proteges, substrats d'interconnexion proteges comportant de tels circuits et procede d'obtention desdits circuits et substrats
DE2748523A1 (de) * 1977-10-28 1979-05-03 Siemens Ag Epoxid-niederdruckpressmasse
DE2922005A1 (de) * 1979-05-30 1980-12-04 Siemens Ag Halbleiterbauelement mit passiviertem halbleiterkoerper
US4327369A (en) * 1979-08-06 1982-04-27 Hi-Tech Industries, Inc. Encapsulating moisture-proof coating
JPS6018145B2 (ja) * 1980-09-22 1985-05-09 株式会社日立製作所 樹脂封止型半導体装置
JPS5790967A (en) * 1980-11-27 1982-06-05 Nec Corp Semiconductor device sealed with resin
US4330637A (en) * 1981-01-05 1982-05-18 Western Electric Company, Inc. Encapsulated electronic devices and encapsulating compositions
JPS57128948A (en) * 1981-02-02 1982-08-10 Sharp Corp Electronic part
US4388132A (en) * 1981-06-01 1983-06-14 Burroughs Corporation Method of attaching a protective film to an integrated circuit
DE3222791A1 (de) * 1982-06-18 1983-12-22 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleiter-bauelementen
JPS59172253A (ja) * 1983-03-18 1984-09-28 Mitsubishi Electric Corp 半導体装置
DE3310654A1 (de) * 1983-03-24 1984-09-27 Standard Elektrik Lorenz Ag, 7000 Stuttgart Verfahren zum versiegeln von flachen hybridbausteinen

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11914293B2 (en) 2017-01-31 2024-02-27 Flint Group Germany Gmbh Radiatioin-curable mixture containing low-functionalised, partially saponified polyvinyl acetate

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EP0202279B1 (de) 1989-08-02
JPS62500900A (ja) 1987-04-09
DE3442131A1 (de) 1986-05-22
DE3442131C2 (enExample) 1988-12-01
US4784872A (en) 1988-11-15
WO1986003055A1 (en) 1986-05-22
EP0202279A1 (de) 1986-11-26

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