DE4101042C1 - Contact and encapsulation of micro-circuits using solder laser - and laser transparent contact film segments with conductor sheets of solderable material, geometrically associated with solder protuberances - Google Patents
Contact and encapsulation of micro-circuits using solder laser - and laser transparent contact film segments with conductor sheets of solderable material, geometrically associated with solder protuberancesInfo
- Publication number
- DE4101042C1 DE4101042C1 DE4101042A DE4101042A DE4101042C1 DE 4101042 C1 DE4101042 C1 DE 4101042C1 DE 4101042 A DE4101042 A DE 4101042A DE 4101042 A DE4101042 A DE 4101042A DE 4101042 C1 DE4101042 C1 DE 4101042C1
- Authority
- DE
- Germany
- Prior art keywords
- laser
- contact
- solder
- soldering
- cutouts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15157—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
Die Erfindung bezieht sich auf ein Verfahren zur Kontaktierung und Verkap selung von Mikroschaltungen gemäß dem Oberbegriff des Anspruchs 1.The invention relates to a method for contacting and capping selection of microcircuits according to the preamble of claim 1.
Solche Verfahren sind in den verschiedensten Ausführungsformen bekannt ge worden. So sind beispielsweise durch die Anmelderin in den Druckschriften DE 34 42 131 A1 und DE 37 25 269 A1 Verfahren zum Einkapseln von mikroelektroni schen Halbleiter- und Schichtschaltungen bekanntgeworden, wobei im einem Fall die auf einen Substrat befindlichen Halbleiterbauelemente mit einer weichen, siegelfähigen Kunststoffschicht übergossen, mit einer Kunst stoff-Metall-Verbundfolie abgedeckt und anschließend mit einer temperatur beständigen, harten Kunstharzvergußmasse verkapselt werden, während im zweiten Fall zur Verhinderung eines Eindiffundierens von Feuchte und kor rosiven Gasen vorgeschlagen wird, daß die mikroelektronische Schichtschal tung an den zu verkapselnden Stellen beim letzten Dielektrikumsdruck mit einem Isolierkranz bedruckt und in speziellen Maßnahmen aufgelötet wird.Such methods are known in various embodiments been. For example, by the applicant in the publications DE 34 42 131 A1 and DE 37 25 269 A1 Process for encapsulating microelectronics rule semiconductor and layer circuits become known, in one Case the semiconductor components located on a substrate with a covered with a soft, sealable plastic layer, with an art Fabric-metal composite film covered and then with a temperature resistant, hard synthetic resin potting compound are encapsulated, while in second case to prevent diffusion of moisture and cor it is proposed that the microelectronic layered scarf at the points to be encapsulated during the last dielectric pressure printed on an insulating ring and soldered in special measures.
Ein Verfahren nach dem Oberbegriff des Anspruchs 1 ist aus der Druck schrift "Feinwerktechnik & Meßtechnik", 1989, Bd. 97, H. 11, S. 507-508 be kannt.A method according to the preamble of claim 1 is from the print font "Feinwerktechnik & Meßtechnik", 1989, Vol. 97, H. 11, pp. 507-508 be knows.
Aus der Druckschrift EP 01 13 895 A1 ist es bekannt, durch eine licht durchlässige Trägerfolie einander gegenüberliegende Verdrahtungen durch einen Laserstrahl miteinander zu verlöten.From the document EP 01 13 895 A1 it is known by a light permeable carrier foil through opposing wiring to solder a laser beam together.
Aus JP 1-23 543 A. in "Patents Abstracts of Japan", E-757, 1989, Vol. 13, Nr. 201 ist es bekannt, Löthöcker eines in einer Vertiefung eines Sub strats angeordneten Bauelements durch Laser-Löten mit den Elektroden einer Leiterplatte zu verbinden. Alle Ausführungsformen des Standes der Technik sind für das Aufbringen der Löthöcker mit einem rechnergesteuerten Löt drahtvorschub nur für größere Durchmesserdimensionen verwendbar.From JP 1-23 543 A. in "Patents Abstracts of Japan", E-757, 1989, Vol. 13, No. 201 it is known to solder bumps one in a recess of a sub Strats arranged component by laser soldering with the electrodes of one Connect circuit board. All embodiments of the prior art are for the application of the solder bumps with a computer-controlled solder wire feeder can only be used for larger diameter dimensions.
Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren der eingangs ge nannten Art zu schaffen, das berührungslos eine gleichzeitige Kontaktierung und Verkapselung einer hochpoligen Mikroelektronikschaltung gewährleistet und auch für Löthöcker mit einem Durchmesser von weniger als 0,1 mm einsetzbar ist, und außerdem den Einsatz von Schaltun gen hoher Anschluß- und Packungsdichte erlaubt.The invention has for its object a method of ge called kind to create the contactless a simultaneous Contacting and encapsulation of a multi-pin microelectronic circuit guaranteed and also for soldering bumps with a diameter of less than 0.1 mm can be used, and also the use of Schaltun allowed for high connection and packing density.
Diese Aufgabe wird durch die im Anspruch 1 aufgezeigten Maßnahmen ge löst. In den Unteransprüchen sind Ausgestaltungen und Weiterbildungen angegeben und in der nachfolgenden Beschreibung ist ein Ausführungsbei spiel erläutert und in den Figuren der Zeichnung skizziert. Es zeigen:This object is achieved by the measures outlined in claim 1 solves. Refinements and developments are in the subclaims and in the description below is an embodiment game explained and sketched in the figures of the drawing. Show it:
Fig. 1 ein Schemabild in einer Seitenansicht eines Ausführungsbeispiels für eine Mehrlagenverkapselung und deren Verbindung, Fig. 1 is a schematic picture in side view of an embodiment of a Mehrlagenverkapselung and their connection,
Fig. 2 eine perspektivische Ansicht in Explosionsdarstellung des Aus führungsbeispiels gemäß Fig. 1, Fig. 2 is a perspective exploded view of the off guidance example according to Fig. 1,
Fig. 3 eine Draufsicht auf die Mikroschaltung gemäß Fig. 1 (beispiels weise IC) in der fixierten Lage auf einem 8, 16, 32 oder 64 mm Film F, Fig. 3 is a plan view of the micro-circuit according to Fig. 1 (Example as IC) mm in the fixed location on an 8, 16, 32 or 64 film F,
Fig. 4 einen Schnitt entlang der Linie A-A des Ausführungsbeispiels ge mäß Fig. 1 in verschweißtem und verkapseltem Zustand. Fig. 4 shows a section along the line AA of the embodiment according to FIG. 1 in the welded and encapsulated state.
An dem in den Fig. 1 und 2 veranschaulichten Ausführungsbeispiel soll das erfindungsgemäße Verfahren zur gleichzeitigen Kontaktierung und Ver kapselung eines IC′s in einem Arbeitsgang erläutert werden. Der IC 10 wird mit sogenannten Löthöckern 11a, 11b, . . . 11n in unterschiedlicher feldartiger Anordnung und unterschiedlicher Höhe mittels eines Lötlasers versehen, wobei die IC′s 10 auf einen Kontaktfilmset F von 8, 16, 32 oder 64 mm Breite auf- und abspulbar fixiert sind. Den un terschiedlich dimensionierten und in Reihen angeordneten Löthöckern 11a bis 11n sind nun Kontaktfolienausschnitte 12a, 12b, . . . 12n zugeordnet, die sich durch eine IR-Lasertransparenz, einen geringen Ausdehnungskoef fizienten, hohe Flexibilität und eine wärmestabile Verkleb- und Verlöt barkeit auszeichnen. Diese Kontaktfolien 12a bis 12n sind mit Leiterbah nen 14a, 14b, . . . 14n aus verlötbarem Material, wie beispielsweise Cu, Ag-Pd usw. versehen. Sie sind in ihrer geometrischen Form - die aus den Figuren der Zeichnung deutlich erkennbar ist - einerseits den Löthöckern und andererseits den Substratanschlüssen 13a, 13b, . . . 13n entsprechend angepaßt. Die Kontaktfolien selbst können aus Polyimid/Cu-Folien oder aber auch aus vor- oder ausgesinterten "Green-sheet-Glaskeramikfolien" mit Ag-Pd-Leiterbahnen gebildet sein.On the embodiment illustrated in FIGS . 1 and 2, the inventive method for simultaneous contacting and encapsulation of an IC's will be explained in one operation. The IC 10 is with so-called solder bumps 11 a, 11 b,. . . 11 n in a different field-like arrangement and at different heights by means of a soldering laser, the IC's 10 being fixed on a contact film set F of 8, 16, 32 or 64 mm in width so that they can be unwound and unwound. The un differently dimensioned and arranged in rows solder bumps 11 a to 11 n are now contact foil cutouts 12 a, 12 b,. . . 12 n assigned, which are characterized by IR laser transparency, a low coefficient of expansion, high flexibility and a heat-stable adhesive and solderability. These contact foils 12 a to 12 n are with conductor tracks 14 a, 14 b,. . . 14 n made of solderable material, such as Cu, Ag-Pd etc. provided. They are in their geometric shape - which can be clearly seen from the figures of the drawing - on the one hand the solder bumps and on the other hand the substrate connections 13 a, 13 b,. . . 13 n adjusted accordingly. The contact foils themselves can be formed from polyimide / Cu foils or else from pre-sintered or sintered "green sheet glass ceramic foils" with Ag-Pd conductor tracks.
Die flächenmäßige Ausbildung jeder Kontaktfolie ist so gehalten, daß sie der ihr zugeordneten Löthöckerreihe entsprechend zugeschnitten ist. Über ein Positioniersystem, das ein X/Y-Tisch, ein Roboter mit Visionssystem usw. sein kann, werden die verschiedenen Kontaktfolien nacheinander von außen nach innen den Löthöckerreihen zugeordnet und mit den Lötlaser die Kontakte 11a bis 11n verlötet und die Kontaktfolien 12a bis 12n unter einander verklebt oder verschweißt. Es wird also - gemäß den Fig. 1 und 2 - zuerst die Kontaktfolie 12n mit den Kontaktreihen 11n und den Lei terbahnen 14n sowohl der Kontaktfolie 12n als auch des Substrat-Inlets 13n verschweißt. Dann erfolgt die Positionierung der Kontaktfolie 12b, die entsprechend der Löthöckerreihe 11b zugeschnitten ist und der vorbe schriebene Lötvorgang etc. wiederholt sich.The areal design of each contact foil is such that it is cut according to the row of solder bumps assigned to it. A positioning system that may be a X / Y table, a robot vision system, etc., the various contact sheets are assigned sequentially from outside to inside the Löthöckerreihen and a brazed to the Lötlaser the contacts 11 to 11 n and the contact films 12 a glued or welded to each other up to 12 n. It is - according to FIGS. 1 and 2 - first the contact foil 12 n with the contact rows 11 n and the conductor tracks 14 n both the contact foil 12 n and the substrate inlet 13 n welded. Then there is the positioning of the contact foil 12 b, which is cut according to the row of solder bumps 11 b and the previously described soldering process etc. is repeated.
Das filmförmige Trägersubstrat F wird entsprechend den vorbeschriebenen Kontaktfolien 12a bis 12n und dem mikroelektronischen Schaltelement 10 stufenförmig ausgebildet. Die durch die Substrat-Inlets 13a bis 13n ent standenen "Stufen" können durch mehrlagig angeordnete Polyimid-Kupfer leiter-Lagenschaltungen, Leiterplatten oder Keramik-Multilayer aus Kera mik-Greensheets mit aufgesinterten Leiterbahnen aus Ag-Pd oder ähnlichem gebildet werden. Löthöcker 11, Kontaktfolien 12 Leiterbahnen 14 und Sub strat-Inlets 13 werden nun mit dem Laser verlötet und verklebt.The film-shaped carrier substrate F is formed in a step-like manner in accordance with the contact foils 12 a to 12 n described above and the microelectronic switching element 10 . The resulting through the substrate inlets 13 a to 13 n "stages" can be formed by multilayer polyimide copper conductor layer circuits, circuit boards or ceramic multilayers made of ceramic greensheets with sintered conductor tracks made of Ag-Pd or the like. Solder bumps 11 , contact foils 12 conductor tracks 14 and sub strat inlets 13 are now soldered and glued with the laser.
Die Löthöcker können vorteilhaft anstelle aus Au, Cu oder Pb-Sn auch aus Pd galvanisch oder - bei kleinen Dimensionen - stromlos hergestellt wer den. Palladium läßt sich gegenüber Au mit dem Laser wesentlich besser unter Verwendung von Sn-Loten verlöten, da die Absorption bei der Wel lenlänge λ=1064 nm bei 40% statt bei 5% liegt. The solder bumps can also advantageously be made of Au, Cu or Pb-Sn Pd galvanically or - in the case of small dimensions - without current the. Palladium is much better compared to Au with the laser using Sn solders, since the absorption at Wel lenlength λ = 1064 nm is 40% instead of 5%.
Der Laser ist vorzugsweise ein temperatur-, positions- oder rechnerge steuerter cw:YAG-Laser, der weitgehend Kunststoff-Folien oder GFK-Epo xy-, Al2O3- und Si-Substrate durchstrahlt und temperaturgesteuerte Mikroverlötungen punktuell (< 50 m) sowie durch Scanning des Laser strahls Folienverschweißungen und Folienverklebungen durchführt.The laser is preferably a temperature, position or computer controlled cw: YAG laser, which largely shines through plastic foils or GRP epoxy, Al 2 O 3 and Si substrates and selectively controls temperature-controlled micro soldering (<50 m) and by scanning the laser beam, foil welding and foil bonding is carried out.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4101042A DE4101042C1 (en) | 1991-01-16 | 1991-01-16 | Contact and encapsulation of micro-circuits using solder laser - and laser transparent contact film segments with conductor sheets of solderable material, geometrically associated with solder protuberances |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4101042A DE4101042C1 (en) | 1991-01-16 | 1991-01-16 | Contact and encapsulation of micro-circuits using solder laser - and laser transparent contact film segments with conductor sheets of solderable material, geometrically associated with solder protuberances |
Publications (1)
Publication Number | Publication Date |
---|---|
DE4101042C1 true DE4101042C1 (en) | 1992-02-20 |
Family
ID=6423077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE4101042A Expired - Lifetime DE4101042C1 (en) | 1991-01-16 | 1991-01-16 | Contact and encapsulation of micro-circuits using solder laser - and laser transparent contact film segments with conductor sheets of solderable material, geometrically associated with solder protuberances |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE4101042C1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4316175A1 (en) * | 1993-05-14 | 1994-11-17 | Daimler Benz Ag | Soldered connection and soldering method |
EP0683513A1 (en) * | 1994-04-26 | 1995-11-22 | International Business Machines Corporation | Electronic package with multilevel connections |
WO1996024162A1 (en) * | 1995-02-02 | 1996-08-08 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Chip housing and process for producing it |
EP0898311A2 (en) * | 1997-08-20 | 1999-02-24 | Nec Corporation | Surface mounting type semiconductor package mounted on a multilayer mounting substrate |
FR2890235A1 (en) * | 2005-08-30 | 2007-03-02 | Commissariat Energie Atomique | Hybridization method of electronic component e.g. x-ray or infrared radiation sensors, involves forming protrusions of larger size on pads of electronic component |
CN110970396A (en) * | 2018-09-28 | 2020-04-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming a semiconductor device |
US11211318B2 (en) | 2018-09-28 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump layout for coplanarity improvement |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0113895A1 (en) * | 1982-12-21 | 1984-07-25 | Siemens Aktiengesellschaft | Method of laser soldering of flexible wirings |
DE3442131A1 (en) * | 1984-11-17 | 1986-05-22 | Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn | METHOD FOR ENCODING MICROELECTRONIC SEMICONDUCTOR AND LAYER CIRCUITS |
DE3725269A1 (en) * | 1987-07-30 | 1989-02-09 | Messerschmitt Boelkow Blohm | METHOD FOR ENCODING MICROELECTRONIC SEMICONDUCTOR AND LAYER CIRCUITS |
-
1991
- 1991-01-16 DE DE4101042A patent/DE4101042C1/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0113895A1 (en) * | 1982-12-21 | 1984-07-25 | Siemens Aktiengesellschaft | Method of laser soldering of flexible wirings |
DE3442131A1 (en) * | 1984-11-17 | 1986-05-22 | Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn | METHOD FOR ENCODING MICROELECTRONIC SEMICONDUCTOR AND LAYER CIRCUITS |
DE3725269A1 (en) * | 1987-07-30 | 1989-02-09 | Messerschmitt Boelkow Blohm | METHOD FOR ENCODING MICROELECTRONIC SEMICONDUCTOR AND LAYER CIRCUITS |
Non-Patent Citations (3)
Title |
---|
Feinwerktechnik & Meßtechnik, 1989, Bd. 97, H. 11, S. 507-508 * |
IBM Technical Disclosure Bulletin, 1986, Vol. 29, Nr. 2, S. 916-918 * |
JP 1-23543 A. In: Patents Abstracts of Japan, E-757, 1989, Vol. 13, Nr. 201 * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4316175A1 (en) * | 1993-05-14 | 1994-11-17 | Daimler Benz Ag | Soldered connection and soldering method |
EP0683513A1 (en) * | 1994-04-26 | 1995-11-22 | International Business Machines Corporation | Electronic package with multilevel connections |
WO1996024162A1 (en) * | 1995-02-02 | 1996-08-08 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Chip housing and process for producing it |
EP0898311A2 (en) * | 1997-08-20 | 1999-02-24 | Nec Corporation | Surface mounting type semiconductor package mounted on a multilayer mounting substrate |
EP0898311A3 (en) * | 1997-08-20 | 2000-05-17 | Nec Corporation | Surface mounting type semiconductor package mounted on a multilayer mounting substrate |
FR2890235A1 (en) * | 2005-08-30 | 2007-03-02 | Commissariat Energie Atomique | Hybridization method of electronic component e.g. x-ray or infrared radiation sensors, involves forming protrusions of larger size on pads of electronic component |
EP1764828A1 (en) * | 2005-08-30 | 2007-03-21 | Commissariat A L'energie Atomique | Method for hybridizing two devices using solder balls of different size and device resulting therefrom |
US7938311B2 (en) | 2005-08-30 | 2011-05-10 | Commissariat A L'energie Atomique | Method for hybridization of two components by using different sized solder protrusions and a device that uses two components hybridized according to this method |
CN110970396A (en) * | 2018-09-28 | 2020-04-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming a semiconductor device |
US11211318B2 (en) | 2018-09-28 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump layout for coplanarity improvement |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69432010T2 (en) | Provide it with soldering balls | |
DE112006000505B4 (en) | Semiconductor device manufacturing | |
DE69534543T2 (en) | Semiconductor arrangement, mounting substrate for the semiconductor device and method for replacing the semiconductor device | |
DE69431740T2 (en) | Multi-layer wiring board and its manufacture | |
DE3888476T2 (en) | Electrical contact points and housings provided with them. | |
DE102004031920B4 (en) | Multi-chip bag and manufacturing process | |
DE69414753T2 (en) | Assembly device and method for connecting miniaturized electronic components by means of bump connections | |
DE3616494A1 (en) | INTEGRATED CIRCUIT BOX AND METHOD FOR PRODUCING AN INTEGRATED CIRCUIT BOX | |
DE10033977A1 (en) | Intermediate coupling structure for mounting semiconductor chip on printed circuit board has conductor paths between contact pads and bonding pads on opposite sides of dielectric body | |
DE60032067T2 (en) | Multilayer printed circuit board and method for its production | |
DE10301512A1 (en) | Reduced chip package and process for its manufacture | |
EP1532681A1 (en) | Multi-layer circuit carrier and production thereof | |
DE3824008A1 (en) | ELECTRONIC CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF | |
DE4133183A1 (en) | CCD housing structure assembly - uses automatically bondable foil with numerous outer and inner leads, and chip bonding straps | |
DE4338432B4 (en) | Semiconductor integrated circuit package, manufacturing method therefor, and assembly method therefor | |
EP1008231A2 (en) | Power module with a circuit arrangement comprising active semiconductor components and passive components, and method for producing same | |
DE60114338T2 (en) | Production method for optical semiconductor module | |
DE10127381A1 (en) | Assembly clamp device for multilayer semiconducting component is rotated to position relative to mother substrate and removed after intermediate connections have been made | |
DE4101042C1 (en) | Contact and encapsulation of micro-circuits using solder laser - and laser transparent contact film segments with conductor sheets of solderable material, geometrically associated with solder protuberances | |
DE2640613C2 (en) | Method and device for contacting circuit components in a layer circuit | |
DE69118308T2 (en) | Method of making an electrical connection for an integrated circuit | |
DE19820319A1 (en) | Substrate-supported chip component production | |
EP0303272A2 (en) | Printed circuits for electronics | |
DE10162676B4 (en) | Electronic component with a semiconductor chip and a rewiring plate and system carrier for a plurality of electronic components and method for producing the same | |
DE102006024147B3 (en) | An electronic module including a semiconductor device package and a semiconductor chip and method of making the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8100 | Publication of the examined application without publication of unexamined application | ||
D1 | Grant (no unexamined application published) patent law 81 | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: DEUTSCHE AEROSPACE AG, 8000 MUENCHEN, DE |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: TEMIC TELEFUNKEN MICROELECTRONIC GMBH, 74072 HEILB |
|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: TEMIC TELEFUNKEN MICROELECTRONIC GMBH, 90411 NUERN |
|
8339 | Ceased/non-payment of the annual fee |