JPH06101466B2 - シリコン層上に2酸化シリコンの絶縁誘電体層を作る方法 - Google Patents
シリコン層上に2酸化シリコンの絶縁誘電体層を作る方法Info
- Publication number
- JPH06101466B2 JPH06101466B2 JP58213177A JP21317783A JPH06101466B2 JP H06101466 B2 JPH06101466 B2 JP H06101466B2 JP 58213177 A JP58213177 A JP 58213177A JP 21317783 A JP21317783 A JP 21317783A JP H06101466 B2 JPH06101466 B2 JP H06101466B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- silicon layer
- silicon dioxide
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H10P14/6308—
Landscapes
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44137282A | 1982-11-12 | 1982-11-12 | |
| US441372 | 1982-11-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59103347A JPS59103347A (ja) | 1984-06-14 |
| JPH06101466B2 true JPH06101466B2 (ja) | 1994-12-12 |
Family
ID=23752622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58213177A Expired - Lifetime JPH06101466B2 (ja) | 1982-11-12 | 1983-11-11 | シリコン層上に2酸化シリコンの絶縁誘電体層を作る方法 |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH06101466B2 (enExample) |
| DE (1) | DE3340583A1 (enExample) |
| FR (1) | FR2536208B1 (enExample) |
| GB (1) | GB2131407B (enExample) |
| IT (1) | IT1171798B (enExample) |
| SE (1) | SE500975C2 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814291A (en) * | 1986-02-25 | 1989-03-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making devices having thin dielectric layers |
| US4874716A (en) * | 1986-04-01 | 1989-10-17 | Texas Instrument Incorporated | Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface |
| EP0281233A1 (en) * | 1987-01-30 | 1988-09-07 | AT&T Corp. | Improved formation of dielectric on deposited silicon |
| US5851871A (en) * | 1987-12-23 | 1998-12-22 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated capacitors in MOS technology |
| DE69030775T2 (de) * | 1989-02-14 | 1997-11-13 | Seiko Epson Corp | Herstelllungsverfahren einer Halbleitervorrichtung |
| EP0545585A3 (en) * | 1991-12-03 | 1996-11-06 | American Telephone & Telegraph | Integrated circuit fabrication comprising a locos process |
| US5712177A (en) * | 1994-08-01 | 1998-01-27 | Motorola, Inc. | Method for forming a reverse dielectric stack |
| US5665620A (en) * | 1994-08-01 | 1997-09-09 | Motorola, Inc. | Method for forming concurrent top oxides using reoxidized silicon in an EPROM |
| EP1192647B1 (en) * | 1999-06-25 | 2010-10-20 | Massachusetts Institute Of Technology | Oxidation of silicon on germanium |
| CN112992672B (zh) * | 2019-12-16 | 2022-10-14 | 山东有研半导体材料有限公司 | 一种硅基二氧化硅背封薄膜的制备方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3900345A (en) * | 1973-08-02 | 1975-08-19 | Motorola Inc | Thin low temperature epi regions by conversion of an amorphous layer |
| JPS5910060B2 (ja) * | 1976-03-01 | 1984-03-06 | 株式会社日立製作所 | 半導体装置の製造方法 |
| IT1089298B (it) * | 1977-01-17 | 1985-06-18 | Mostek Corp | Procedimento per fabbricare un dispositivo semiconduttore |
| US4166919A (en) * | 1978-09-25 | 1979-09-04 | Rca Corporation | Amorphous silicon solar cell allowing infrared transmission |
| JPS55115341A (en) * | 1979-02-28 | 1980-09-05 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS5676537A (en) * | 1979-11-27 | 1981-06-24 | Fujitsu Ltd | Manufacture of semiconductor device |
| US4479831A (en) * | 1980-09-15 | 1984-10-30 | Burroughs Corporation | Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment |
| US4358326A (en) * | 1980-11-03 | 1982-11-09 | International Business Machines Corporation | Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing |
| US4441249A (en) * | 1982-05-26 | 1984-04-10 | Bell Telephone Laboratories, Incorporated | Semiconductor integrated circuit capacitor |
-
1983
- 1983-11-03 GB GB08329380A patent/GB2131407B/en not_active Expired
- 1983-11-04 SE SE8306071A patent/SE500975C2/sv unknown
- 1983-11-10 DE DE19833340583 patent/DE3340583A1/de active Granted
- 1983-11-10 FR FR8317930A patent/FR2536208B1/fr not_active Expired
- 1983-11-11 JP JP58213177A patent/JPH06101466B2/ja not_active Expired - Lifetime
- 1983-11-11 IT IT23691/83A patent/IT1171798B/it active
Also Published As
| Publication number | Publication date |
|---|---|
| DE3340583A1 (de) | 1984-05-17 |
| FR2536208A1 (fr) | 1984-05-18 |
| GB8329380D0 (en) | 1983-12-07 |
| GB2131407A (en) | 1984-06-20 |
| SE8306071L (sv) | 1984-05-13 |
| GB2131407B (en) | 1987-02-04 |
| IT1171798B (it) | 1987-06-10 |
| IT8323691A0 (it) | 1983-11-11 |
| DE3340583C2 (enExample) | 1993-04-29 |
| FR2536208B1 (fr) | 1987-03-20 |
| JPS59103347A (ja) | 1984-06-14 |
| SE500975C2 (sv) | 1994-10-10 |
| SE8306071D0 (sv) | 1983-11-04 |
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