GB2131407A - Method of formation of silicon dioxide layer - Google Patents
Method of formation of silicon dioxide layer Download PDFInfo
- Publication number
- GB2131407A GB2131407A GB08329380A GB8329380A GB2131407A GB 2131407 A GB2131407 A GB 2131407A GB 08329380 A GB08329380 A GB 08329380A GB 8329380 A GB8329380 A GB 8329380A GB 2131407 A GB2131407 A GB 2131407A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- silicon dioxide
- silicon
- silicon layer
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 90
- 239000000377 silicon dioxide Substances 0.000 title claims abstract description 46
- 235000012239 silicon dioxide Nutrition 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015572 biosynthetic process Effects 0.000 title description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 229910052760 oxygen Inorganic materials 0.000 claims description 14
- 239000001301 oxygen Substances 0.000 claims description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 230000005684 electric field Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000003607 modifier Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 239000000523 sample Substances 0.000 description 34
- 238000012360 testing method Methods 0.000 description 31
- 229920005591 polysilicon Polymers 0.000 description 26
- 230000015556 catabolic process Effects 0.000 description 12
- 230000008021 deposition Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910000077 silane Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 238000005269 aluminizing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Recrystallisation Techniques (AREA)
Abstract
A method of forming a layer of silicon dioxide having a high dielectric strength and low leakage current comprises depositing an amorphous silicon layer on a substrate at a temperature of less than 580 DEG C and oxidizing a portion of the amorphous silicon layer. This silicon dioxide layer may be incorporated in a semiconductor device having a high dielectric strength.
Description
SPECIFICATION
Method of formation of silicon dioxide layer
This invention is a method of formation upon deposited silicon of silicon dioxide having a high dielectric strength and low leakage current.
Multilevel polycrystalline silicon (polysilicon) structures, consisting of polysilicon layers separated by insulating dielectrics, are used extensively in silicon devices such as charge-coupled devices, and integrated circuit structures such as capacitors, EEPROM and CMOS devices. Typically, the polysilicon layers, which may be doped with phosphorus in order to lower their resistivity, are formed by low pressure chemical vapor deposition (LPCVD) at a substrate temperature of about 6200C. The insulating dielectric is typically silicon dioxide formed either by thermal oxidation of the underlying polysilicon layer or by chemical vapor deposition onto the polysilicon layer. Thermally grown silicon dioxide is preferred because of the simplicity of the processing and because of the purity of the oxide obtained.
It is well known, however, that the insulating properties of silicon dioxide thermally grown on an underlying polysilicon layer are inferior to those of silicon dioxide thermally grown on single-crystal silicon. In particular, such oxides have a lower dielectric strength (the electric field at which destructive breakdown occurs) and exhibit an enhanced leakage current for a given applied electric field. These affects have been attributed to the surface roughness of the polysilicon-silicon dioxide interface arising from the graininess of the polysilicon and the resulting texturing of the polysilicon surface. Surface roughness produces a variation in the local electric field at the silicon-silicon dioxide interface which enhances electron injection into the oxide.
Silicon, deposited from an atmosphere containing silicon onto a substrate at a temperature less than 5800C, forms an amorphous silicon layer having an extremely smooth surface. Annealing of this film at a temperature between about 9000C and 1 0000C converts the amorphous silicon from the amorphous state to a polycrystalline state having an average grain size of about 0.08 micrometers (cm). The surprising result of this process is that the surface of the polysilicon remains extremely smooth in spite of the fact that the grain size in the polysilicon layer initially deposited in the amorphous state is significantly greater than that in the layer deposited in the polycrystalline state.
The present invention is a method of fabricating a silicon dioxide layer comprising the steps of depositing a layer of amorphous silicon on a substrate at a temperature less than about 5800C and oxidizing the layer.
The invention also includes semiconductor devices having a silicon dioxide layer on a polysilicon layer wherein the silicon dioxide layer is formed by thermal oxidation of amorphous silicon deposited at a temperature less than 5800C.
In the drawing:
Figure 1 is a cross-sectional view of a semiconductor device incorporating the present invention.
Figure 2 is a schematic illustration of the testing apparatus used to measure the properties of the silicon dioxide layer of the present invention.
Figures 3 and 4 are histograms showing the breakdown voltage of silicon dioxide formed on amorphous silicon and polysilicon layers.
Figure 1 shows a portion 10 of a semiconductor device having a gate structure thereon which is typical of that found in a charge-coupled device. The portion 10 includes a single-crystal silicon body 12 having a major surface 14. A gate oxide 1 6, typically formed by thermal oxidation of the silicon body 12, overlies the surface 14. A gate structure comprising a plurality of each of three different gates 18, 20 and 22 in a multilevel structure with each gate isolated from the others by a dielectric 24, typically silicon dioxide, overlies the gate oxide 16.
In the prior art, the gates 18, 20 and 22 are typically composed of polysilicon deposited in the polycrystalline state by LPCVD from an atmosphere containing silicon and a dopant preferably phosphorus, at a temperature of 6200C or greater. The dielectric isolation between the gates is formed by heating the polysilicon layer in a dry oxygen atmosphere at a temperature of between about 9000C and 1 000C, or in steam at a temperature of between about 800 and 9000 C. Typically, the atmosphere also contains about 3 percent by volume of gaseous HCI.
The method of the present invention comprises depositing amorphous silicon, typically by LPCVD from an atmosphere containing silicon in the form of silane diluted with nitrogen, although other deposition methods are not excluded, where the temperature of the substrate is less than 5800 C, typically between about 5500C and 5750C and preferably about 5600 C. subsequently, the amorphous silicon layer is converted to a polycrystalline state by annealing at a temperature greater than about 6000C and preferably between about 900 and 10000 C. The substrate upon which the amorphous silicon is deposited is typically a body of single-crystal silicon having a gate oxide layer thereon.
The amorphous silicon layer may be doped with a conductivity modifier, typically phosphorus, by addition of a phosphorus-containing compound to the atmosphere during the deposition process. We have found, however, that it is preferable to dope the amorphous silicon in a subsequent step since the surface of the resulting doped silicon layer is smoother than if the doping is done simultaneously with the deposition of the amorphous silicon layer.
The amorphous silicon layer may be doped in a subsequent step using ion implantation or diffusion from an atmosphere containing the dopant using techniques well known in the art. For diffusion doping, an atmosphere containing POCI3 may be used with the amorphous silicon layer heated to a temperature between about 800 and 11 000C. With ion implantation the subsequent oxidation step activates the dopant.
An amorphous silicon layer doped with phosphorus may be converted to polysilicon by annealing in an atmosphere of nitrogen containing about 0.5 percent oxygen at a temperature between about 8500C and 10000C. The small oxygen concentration forms a thin glass layer on the surface and prevents the escape of phosphorus and the formation of a nitride on the surface. Diffusion doping of the amorphous silicon layer in the POCI3 atmosphere also results in the formation of a thin glass layer on the surface of the layer. In either case the glass is typically between 2 and 10 nm thick and is heavily doped with phosphorus. This glass is not a useful insulating dielectric and is removed by etching techniques prior to the formation of a silicon dioxide insulating dielectric.
At this point in the process, the silicon layer is in the amorphous state if the doping of the layer was carried out during the deposition process or by ion implantation. If the layer is doped subsequent to deposition by diffusion, the heating of the layer during the doping process is sufficient to convert the layer to the polycrystalline state at the onset of the doping step. The thermal oxidation step described below is also sufficient to convert the deposited layer from the amorphous to the polycrystalline state.
It has been found that, in spite of the fact that the amorphous silicon layer undergoes a transition to the polycrystalline state at the very beginning of either the doping or oxidation step, a silicon dioxide layer disposed thereon exhibits a suprisingly greater dielectric strength and reduced leakage current than that found for layers disposed on polysilicon which is initially deposited in the polycrystalline state.
Prior to the oxidation step, the deposited silicon layer is typically patterned into a desired configuration, such as one or more electrodes, by removal of a portion of the silicon layer using standard lithographic and etching processes.
The deposited silicon layer, whether in the amorphous or the polycrystalline state, is oxidized by heating in an atmosphere containing steam or dry oxygen as described above. However, use of the dry oxygen atmosphere is preferred.
The silicon dioxide layer is at least about 10 nm thick, typically greater than about 15 nm thick, and is preferably greater than about 25 nm thick.
Silicon dioxide formed according to the method of the invention was tested using the test apparatus illustrated in Figure 2.
A test sample includes a body 40 of single-crystal silicon having a surface 42 with a gate oxide 44 which is 0.3 ,um thick overlying a portion of the surface 42. A gate electrode 46, consisting of a phosphorus-doped silicon layer deposited according to the method of the present invention, overlies the gate oxide 44 and a portion of the surface 42 of the body 40. For convenience, the gate electrode 46 was not patterned. A silicon dioxide layer 48, fabricated according to the method of the present invention, overlies the gate electrode 46. A plurality of test electrodes 50, each consisting of a one millimeter diameter layer of n-type polycrystalline silicon and an aluminum contact to the polycrystalline silicon layer overlies the silicon dioxide layer 48, thereby forming a plurality of test capacitors on the test sample.
The measurement apparatus includes a voltage source 60, a current-limiting series resistor 62 and a probe 64 to provide an electrical connection to one of the plurality of test electrodes 50.
Electrical current flows from the voltage source 60 through the current limiting resistor 62, the probe 64, the test sample and an ammeter 66 to ground potential. A voltmeter 68 is connected across the test sample to measure the voltage drop across it.
The voltage source 60 may provide either a positive or negative voltage to the test electrode 50.
The breakdown voltage and the leakage current for each test capacitor is separately measured with both a positive and a negative voltage on a test electrode. Since the electrical current flow through a test capacitor is primarily due to electron injection into the silicon dioxide from the gate or test electrode, the comparison of the results for the different voltage polarities provides a measure of the quality of the interface between the gate electrode and the silicon dioxide layer thereon.
The following Examples are illustrative of the invention and are not intended to limit the scope of the invention in any way.
Example 1
Three test samples each having a common gate electrode and a plurality of test electrodes, as described above, were prepared by thermal oxidation in a dry oxygen atmosphere. Sample I was an amorphous silicon layer deposited by LPCVD in an atmosphere of silane onto a gate oxide at a temperature of 5600C. The amorphous silicon layer was then doped with phosphorus by diffusion from a POOl3 atmosphere at 9500C for 15 minutes. This treatment also converted the silicon layer to the polycrystalline state having a sheet resistivity of 1 6 Q/C1. This layer was then heated at 1 0000C in an atmosphere of dry oxygen plus three percent HCI for one hour thereby forming a 108 nanometer (nm) thick layer of silicon dioxide on the surface of the silicon layer.
A plurality of test electrodes were formed on the silicon oxide layer by the following steps:
(a) depositing a layer of polysilicon about 700 nanometers thick over the oxide;
(b) doping the polysilicon by diffusion of phorphorus from a POCI3 source.
(c) defining polysilicon dots using standard photoresist and chemical etching techniques;
(d) aluminizing the entire surface including both the polysilicon dots and the exposed silicon
dioxide; and
(e) defining aluminum dots on the polysilicon dots having a smaller diameter than the polysilicon
dots using standard photoresist and chemical etching techniques.
Sample II was formed using the same techniques as for Sample I except that the amorphous silicon layer was deposited at 5600C from an atmosphere containing silane and phosphine, thereby combining the depositing and doping steps. The amorphous silicon layer had a sheet resistivity of 10 #/C. The silicon dioxide layer, formed as for Sample I, was 130 nm thick. The test electrodes were formed on the silicon dioxide layer as described above.
Sample Ill is a comparative sample formed by deposition from an atmosphere containing silane at 6200C followed by doping from a POCI3 atmosphere at 9500C for 15 minutes, thereby forming a conventional polysilicon layer. The silicon dioxide layer, formed as for Sample I, on the polysilicon layer was 95 nm thick and had a resistivity of 18 Q/C1. The test electrodes were also formed as described above for Sample I.
Figures 3(a), (b) and (c) are histograms of the percentages of devices of test Samples I, II and Ill, respectively, having destructive breakdown fields in a given range for positive and negative voltages applied to the test electrode.
From the Figures, it is clear that silicon dioxide formed from a silicon layer deposited in the amorphous state, whether amorphous or polycrystalline when the oxidation is started, have, on averge, about a factor of two higher breakdown field than silicon dioxide formed on silicon deposited in the polycrystalline state.
For the reverse voltage polarity, electron injection occurs from the test electrode. Since the roughness of the gate-silicon dioxide interface is partially removed during the oxide growth, the interface between the test electrode and the oxide will be smoother than that at the gate-silicon dioxide interface. In this case, the difference between the layers deposited in the amorphous state and those deposited in the polycrystalline state is not as great, and a smaller increase in the breakdown voltage is observed.
Sample I has a higher average breakdown voltage than Sample II for both voltage polarities. This result indicates that sequential doping of the amorphous silicon layer is preferred to simultaneous deposition and doping of the silicon layer. This result is surprising in that conversion of the amorphous silicon to polysilicon occurs at the onset of the doping step. Dopant atoms then enter the polysilicon preferentially at the grain boundaries, and the subsequent oxidation occurs preferentially at such boundaries due to the excess dopant. This should cause an increased roughening of the silicon surface.
Example 2
Three test samples, each having a common gate electrode and a plurality of test electrodes as described above, were prepared by thermal oxidation of a portion of the gate electrode in a steam atmosphere. Sample IV, comprising an amorphous silicon gate electrode deposited and doped as in the case of Sample I of Example 1, had a resistivity of about 1 9 S?/O. The silicon dioxide layer formed in the steam atmosphere was 175 nm thick. Sample V was formed using the same techniques as Sample IV except that the amorphous silicon layer was deposited and doped in the same step, as was the case for
Sample II of Example 1. The sheet resistivity of the silicon layer was 10 #/O. The silicon dioxide formed in the steam atmosphere had a thickness of 161 nm.Sample Vl is a comparative sample, corresponding to Sample Ill of Example 1, formed by deposition of a silicon layer in the polycrystalline state at 6200C with subsequent doping at 9500 C. for 15 minutes in a POOl3 atmosphere. The sheet resistivity of the polycrystalline layer was 1 5 S?/o. The silicon dioxide formed in the steam atmosphere at 8500 C. was 200 nm thick.
Figures 4(a), (b) and (c) are histograms of the percentage of devices for test Samples IV, V and Vl, respectively, having breakdown fields in a given range for positive and negative voltages applied to the test electrode. For positive test voltages on the test electrodes, a small, on the order of 25 to 50 percent, increase of the breakdown field is observed. For a negative test voltage on the test electrode, a similar increase in the breakdown field is observed.
A comparison of these breakdown fields with those for Samples l, II and Ill show that, for each type of sample, the breakdown field is consistently higher if the thermal oxidation is carried out in a dry oxygen atmosphere as opposed to a steam atmosphere.
Example 3
Leakage current densities were measured at a constant applied electric field of three megavolts per centimeter on four different samples. The results are shown in the Table.
Sample A was formed by deposition in the amorphous state, doped and oxidized in dry oxygen as in the case of Sample I. The oxide thickness was 160 nm.
Sample B was formed by deposition in the polycrystalline phase, doped and oxidized in dry oxygen as in the case of Sample Ill. The oxide thickness was 130 nm.
Sample C was formed by deposition in the amorphous phase, doped and oxidized in steam as in the case of Sample IV. The oxide thickness was 11 6 nm.
Sample D was formed by deposition in the polycrystalline phase, doped and oxidized in steam as in the case of Sample Vl. The oxide thickness was 80 nm.
Table
Gate Leakage
Sample polarity current density
A (+) 7.5x10-7 amps/cm2 B (+) 1.6x10#4amps"cm2 C (+) 3.1x10-4amps/cm2 D (+) 1.1x10-3amps/cm2 Thus, silicon dioxide layers formed according to the method of the present invention, i.e., on silicon deposited in the amorphous phase and oxidized in dry oxygen, exhibit leakage currents which are greater than three orders of magnitude less than those exhibited by silicon dioxide layers formed by conventional techniques.
Claims (14)
1. A method of fabricating a silicon dioxide insulating dielectric layer on a silicon layer comprising the steps of:
depositing an amorphous silicon layer on a substrate at a temperature less than about 5800 C; and
heating said layer at a temperature between 90000 and 110000 in a dry oxygen atmosphere oxygen to oxidize a portion of said layer and form an insulating dielectric layer.
2. The method of Claim 1 further comprising the step of doping the amorphous silicon layer prior to oxidizing said layer.
3. The method of Claim 2 wherein the steps of depositing and doping the amorphous silicon layer are combined into a single step.
4. The method of Claim 2 wherein the deopant is phosphorus.
5. The method of Claim 1 wherein the step of depositing the amorphous silicon layer is carried out at a temperature between about 55000 and 57500.
6. The method of Claim 5 wherein the step of depositing the amorphous silicon layer is carried out at a temperature of about 5600 C.
7. The method of Claim 7 wherein the step of oxidizing the amorphous silicon layer is carried out at a temperature between 95000 and 105000.
8. In a semiconductor device including a patterned polycrystalline silicon layer with a silicon dioxide layer thereon, the improvement comprising the silicon dioxide layer being formed by thermal oxidation in a dry oxygen atmosphere of a silicon layer deposited at a temperature less than 5800 C.
9. A semiconductor device in accordance with Claim 8 wherein said device further comprises an additional layer of suitable material disposed on said silicon dioxide layer, said silicon dioxide layer therebetween having a thickness less than about 200 nanometers.
10. The article of Claim 8 wherein the silicon layer is deposited at a temperature between about 5500C and 57500.
11. The article of Claim 8 wherein the silicon layer is doped with a conductivity modifier prior to thermal oxidation.
12. In a semiconductor device including a patterned polycrystalline silicon layer with a silicon dioxide layer thereon, the improvement comprising the silicon dioxide layer having a leakage current density less than about 10-6 amperes per square centimeter at an applied electric field of about three megavolts per centimeter.
13. A semiconductor device substantially as described hereinbefore with reference to Figure 1 of the accompanying drawing.
14. A process of forming a silicon dioxide insulating dielectric layer substantially as described hereinbefore with reference to Figures 3 and 4 of the accompanying drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44137282A | 1982-11-12 | 1982-11-12 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8329380D0 GB8329380D0 (en) | 1983-12-07 |
| GB2131407A true GB2131407A (en) | 1984-06-20 |
| GB2131407B GB2131407B (en) | 1987-02-04 |
Family
ID=23752622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08329380A Expired GB2131407B (en) | 1982-11-12 | 1983-11-03 | Method of formation of silicon dioxide layer |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH06101466B2 (en) |
| DE (1) | DE3340583A1 (en) |
| FR (1) | FR2536208B1 (en) |
| GB (1) | GB2131407B (en) |
| IT (1) | IT1171798B (en) |
| SE (1) | SE500975C2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814291A (en) * | 1986-02-25 | 1989-03-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making devices having thin dielectric layers |
| US4874716A (en) * | 1986-04-01 | 1989-10-17 | Texas Instrument Incorporated | Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface |
| US5851871A (en) * | 1987-12-23 | 1998-12-22 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated capacitors in MOS technology |
| WO2001001466A1 (en) * | 1999-06-25 | 2001-01-04 | Massachusetts Institute Of Technology | Oxidation of silicon on germanium |
| US6403497B1 (en) * | 1989-02-14 | 2002-06-11 | Seiko Epson Corporation | Method of manufacturing semiconductor device by two stage heating of deposited noncrystalline semiconductor |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0281233A1 (en) * | 1987-01-30 | 1988-09-07 | AT&T Corp. | Improved formation of dielectric on deposited silicon |
| EP0545585A3 (en) * | 1991-12-03 | 1996-11-06 | American Telephone & Telegraph | Integrated circuit fabrication comprising a locos process |
| US5665620A (en) * | 1994-08-01 | 1997-09-09 | Motorola, Inc. | Method for forming concurrent top oxides using reoxidized silicon in an EPROM |
| US5712177A (en) * | 1994-08-01 | 1998-01-27 | Motorola, Inc. | Method for forming a reverse dielectric stack |
| CN112992672B (en) * | 2019-12-16 | 2022-10-14 | 山东有研半导体材料有限公司 | Preparation method of silicon-based silicon dioxide back sealing film |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3900345A (en) * | 1973-08-02 | 1975-08-19 | Motorola Inc | Thin low temperature epi regions by conversion of an amorphous layer |
| JPS5910060B2 (en) * | 1976-03-01 | 1984-03-06 | 株式会社日立製作所 | Manufacturing method of semiconductor device |
| IT1089298B (en) * | 1977-01-17 | 1985-06-18 | Mostek Corp | PROCEDURE FOR MANUFACTURING A SEMICONDUCTIVE DEVICE |
| US4166919A (en) * | 1978-09-25 | 1979-09-04 | Rca Corporation | Amorphous silicon solar cell allowing infrared transmission |
| JPS55115341A (en) * | 1979-02-28 | 1980-09-05 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS5676537A (en) * | 1979-11-27 | 1981-06-24 | Fujitsu Ltd | Manufacture of semiconductor device |
| US4479831A (en) * | 1980-09-15 | 1984-10-30 | Burroughs Corporation | Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment |
| US4358326A (en) * | 1980-11-03 | 1982-11-09 | International Business Machines Corporation | Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing |
| US4441249A (en) * | 1982-05-26 | 1984-04-10 | Bell Telephone Laboratories, Incorporated | Semiconductor integrated circuit capacitor |
-
1983
- 1983-11-03 GB GB08329380A patent/GB2131407B/en not_active Expired
- 1983-11-04 SE SE8306071A patent/SE500975C2/en unknown
- 1983-11-10 DE DE19833340583 patent/DE3340583A1/en active Granted
- 1983-11-10 FR FR8317930A patent/FR2536208B1/en not_active Expired
- 1983-11-11 JP JP58213177A patent/JPH06101466B2/en not_active Expired - Lifetime
- 1983-11-11 IT IT23691/83A patent/IT1171798B/en active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814291A (en) * | 1986-02-25 | 1989-03-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making devices having thin dielectric layers |
| US4874716A (en) * | 1986-04-01 | 1989-10-17 | Texas Instrument Incorporated | Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface |
| US5851871A (en) * | 1987-12-23 | 1998-12-22 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated capacitors in MOS technology |
| US6403497B1 (en) * | 1989-02-14 | 2002-06-11 | Seiko Epson Corporation | Method of manufacturing semiconductor device by two stage heating of deposited noncrystalline semiconductor |
| WO2001001466A1 (en) * | 1999-06-25 | 2001-01-04 | Massachusetts Institute Of Technology | Oxidation of silicon on germanium |
| US6352942B1 (en) | 1999-06-25 | 2002-03-05 | Massachusetts Institute Of Technology | Oxidation of silicon on germanium |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8329380D0 (en) | 1983-12-07 |
| FR2536208B1 (en) | 1987-03-20 |
| GB2131407B (en) | 1987-02-04 |
| IT1171798B (en) | 1987-06-10 |
| FR2536208A1 (en) | 1984-05-18 |
| SE8306071D0 (en) | 1983-11-04 |
| JPS59103347A (en) | 1984-06-14 |
| DE3340583A1 (en) | 1984-05-17 |
| SE500975C2 (en) | 1994-10-10 |
| JPH06101466B2 (en) | 1994-12-12 |
| SE8306071L (en) | 1984-05-13 |
| IT8323691A0 (en) | 1983-11-11 |
| DE3340583C2 (en) | 1993-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Watanabe et al. | Formation and properties of porous silicon and its application | |
| US4464701A (en) | Process for making high dielectric constant nitride based materials and devices using the same | |
| DE69130263T2 (en) | Process for the production of polycrystalline silicon with a micro-rough surface | |
| US4996081A (en) | Method of forming multiple nitride coating on silicon | |
| Hu | Properties of amorphous silicon nitride films | |
| US7129551B2 (en) | Electronic component having a praseodymium oxide layer and process for fabricating same | |
| JPH0465548B2 (en) | ||
| US5349494A (en) | Semiconductor device with capacitor insulating film and method for fabricating the same | |
| Faraone et al. | Characterization of thermally oxidized n+ polycrystalline silicon | |
| Revesz et al. | Bulk electrical conduction in the buried oxide of SIMOX structures | |
| GB2131407A (en) | Method of formation of silicon dioxide layer | |
| JPH01287942A (en) | Soi semiconductor structure and its manufacture | |
| Ohji et al. | Reliability of nano-meter thick multi-layer dielectric films on poly-crystalline silicon | |
| US6316339B1 (en) | Semiconductor device and production method thereof | |
| Weimann | Oxide and interface properties of anodic oxide MOS structures on III–V compound semiconductors | |
| US3615941A (en) | Method for manufacturing semiconductor device with passivation film | |
| Hickmott et al. | Barrier heights at the polycrystalline silicon‐SiO2 interface | |
| KR100275712B1 (en) | Method of fabrication oxide film of semiconductor device | |
| Shinada et al. | Reduction in polysilicon oxide leakage current by annealing prior to oxidation | |
| King et al. | Polycrystalline silicon resistors for integrated circuits | |
| Lee et al. | Electrode shape effects on oxide conduction in films thermally grown from polycrystalline silicon | |
| KR20030074108A (en) | Semiconductor device and method of manufactuing the same | |
| KR0178992B1 (en) | Method for fabricating capacitor dielectric film of dram | |
| IT8323669A1 (en) | "Automatic polarization control system, with a compensated detection point" | |
| KR960004461B1 (en) | Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20031102 |