JPH0563941B2 - - Google Patents

Info

Publication number
JPH0563941B2
JPH0563941B2 JP9174134A JP7413491A JPH0563941B2 JP H0563941 B2 JPH0563941 B2 JP H0563941B2 JP 9174134 A JP9174134 A JP 9174134A JP 7413491 A JP7413491 A JP 7413491A JP H0563941 B2 JPH0563941 B2 JP H0563941B2
Authority
JP
Japan
Prior art keywords
process diagram
forming
plating layer
circuit
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9174134A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0555401A (ja
Inventor
Hiromi Ogawa
Osamu Fujikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57178663A external-priority patent/JPS5967686A/ja
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP3074134A priority Critical patent/JPH0555401A/ja
Publication of JPH0555401A publication Critical patent/JPH0555401A/ja
Publication of JPH0563941B2 publication Critical patent/JPH0563941B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structure Of Printed Boards (AREA)
JP3074134A 1982-10-12 1991-03-13 プリント配線基板 Granted JPH0555401A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3074134A JPH0555401A (ja) 1982-10-12 1991-03-13 プリント配線基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57178663A JPS5967686A (ja) 1982-10-12 1982-10-12 プリント配線基板とその製造方法
JP3074134A JPH0555401A (ja) 1982-10-12 1991-03-13 プリント配線基板

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP57178663A Division JPS5967686A (ja) 1982-10-12 1982-10-12 プリント配線基板とその製造方法

Publications (2)

Publication Number Publication Date
JPH0555401A JPH0555401A (ja) 1993-03-05
JPH0563941B2 true JPH0563941B2 (enrdf_load_stackoverflow) 1993-09-13

Family

ID=26415269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3074134A Granted JPH0555401A (ja) 1982-10-12 1991-03-13 プリント配線基板

Country Status (1)

Country Link
JP (1) JPH0555401A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753638B2 (en) 2000-02-03 2004-06-22 Calient Networks, Inc. Electrostatic actuator for micromechanical systems
US7728339B1 (en) 2002-05-03 2010-06-01 Calient Networks, Inc. Boundary isolation for microelectromechanical devices
JP4562632B2 (ja) * 2005-09-30 2010-10-13 三洋電機株式会社 回路基板および回路基板の製造方法
US7737368B2 (en) 2005-09-30 2010-06-15 Sanyo Electric Co., Ltd. Circuit board and method of manufacturing circuit board

Also Published As

Publication number Publication date
JPH0555401A (ja) 1993-03-05

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