JPH0560671B2 - - Google Patents

Info

Publication number
JPH0560671B2
JPH0560671B2 JP61005310A JP531086A JPH0560671B2 JP H0560671 B2 JPH0560671 B2 JP H0560671B2 JP 61005310 A JP61005310 A JP 61005310A JP 531086 A JP531086 A JP 531086A JP H0560671 B2 JPH0560671 B2 JP H0560671B2
Authority
JP
Japan
Prior art keywords
insulating film
forming
conductor layer
gate insulating
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61005310A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62163376A (ja
Inventor
Shinji Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61005310A priority Critical patent/JPS62163376A/ja
Priority to US06/941,439 priority patent/US4734887A/en
Priority to KR1019870000077A priority patent/KR900003875B1/ko
Priority to EP87100310A priority patent/EP0236676B1/en
Priority to DE8787100310T priority patent/DE3780484T2/de
Publication of JPS62163376A publication Critical patent/JPS62163376A/ja
Publication of JPH0560671B2 publication Critical patent/JPH0560671B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP61005310A 1986-01-14 1986-01-14 半導体記憶装置の製造方法 Granted JPS62163376A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP61005310A JPS62163376A (ja) 1986-01-14 1986-01-14 半導体記憶装置の製造方法
US06/941,439 US4734887A (en) 1986-01-14 1986-12-15 Erasable programmable read only memory (EPROM) device and a process to fabricate thereof
KR1019870000077A KR900003875B1 (ko) 1986-01-14 1987-01-08 소거가능 프로그래머블 판독전용 메모리장치 및 그의 제조방법
EP87100310A EP0236676B1 (en) 1986-01-14 1987-01-13 Erasable programmable read only memory using floating gate field effect transistors
DE8787100310T DE3780484T2 (de) 1986-01-14 1987-01-13 Loeschbarer programmierbarer nurlesespeicher mit gleitgate-feldeffekttransistoren.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61005310A JPS62163376A (ja) 1986-01-14 1986-01-14 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
JPS62163376A JPS62163376A (ja) 1987-07-20
JPH0560671B2 true JPH0560671B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-09-02

Family

ID=11607698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61005310A Granted JPS62163376A (ja) 1986-01-14 1986-01-14 半導体記憶装置の製造方法

Country Status (5)

Country Link
US (1) US4734887A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0236676B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS62163376A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR900003875B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3780484T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2616576B1 (fr) * 1987-06-12 1992-09-18 Commissariat Energie Atomique Cellule de memoire eprom et son procede de fabrication
JP2618946B2 (ja) * 1987-12-28 1997-06-11 株式会社東芝 不揮発性半導体メモリ装置の製造方法
US5143860A (en) * 1987-12-23 1992-09-01 Texas Instruments Incorporated High density EPROM fabricaiton method having sidewall floating gates
JP2780715B2 (ja) * 1988-03-04 1998-07-30 ソニー株式会社 半導体装置の製造方法
US5268318A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Highly compact EPROM and flash EEPROM devices
FR2633455B1 (fr) * 1988-06-24 1990-08-24 Thomson Csf Matrice photosensible a transfert de trame d.t.c., avec un systeme antieblouissement vertical, et procede de fabrication d'une telle matrice
JPH0265175A (ja) * 1988-08-31 1990-03-05 Toshiba Corp 半導体不揮発性記憶装置及びその製造方法
US5296396A (en) * 1988-12-05 1994-03-22 Sgs-Thomson Microelectronics S.R.L. Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
JPH0821638B2 (ja) * 1989-12-15 1996-03-04 株式会社東芝 不揮発性半導体記憶装置およびその製造方法
JPH088316B2 (ja) * 1990-01-31 1996-01-29 株式会社東芝 紫外線消去型不揮発性半導体メモリ装置
JPH088317B2 (ja) * 1990-04-24 1996-01-29 株式会社東芝 半導体記憶装置及びその製造方法
US5057447A (en) * 1990-07-09 1991-10-15 Texas Instruments Incorporated Silicide/metal floating gate process
KR970000533B1 (ko) * 1990-12-20 1997-01-13 후지쓰 가부시끼가이샤 Eprom 및 그 제조방법
EP0537677B1 (en) * 1991-10-16 1998-08-19 Sony Corporation Method of forming an SOI structure with a DRAM
JP3160966B2 (ja) * 1991-10-16 2001-04-25 ソニー株式会社 Ｓｏｉ基板の製造方法
KR100215840B1 (ko) * 1996-02-28 1999-08-16 구본준 반도체 메모리셀 구조 및 제조방법
JP3583579B2 (ja) 1997-06-06 2004-11-04 株式会社東芝 不揮発性半導体記憶装置およびその製造方法
DE19926500C2 (de) * 1999-06-10 2001-09-20 Infineon Technologies Ag Nichtflüchtige Halbleiter-Speicherzelle mit einer eine hohe relative Dielektrizitätskonstante aufweisenden dielektrischen Schicht und Verfahren zu deren Herstellung
US6744094B2 (en) 2001-08-24 2004-06-01 Micron Technology Inc. Floating gate transistor with horizontal gate layers stacked next to vertical body
US7288821B2 (en) * 2005-04-08 2007-10-30 International Business Machines Corporation Structure and method of three dimensional hybrid orientation technology

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258466A (en) * 1978-11-02 1981-03-31 Texas Instruments Incorporated High density electrically programmable ROM
JPS5929155B2 (ja) * 1979-11-12 1984-07-18 富士通株式会社 半導体記憶装置
US4493057A (en) * 1980-01-07 1985-01-08 Texas Instruments Incorporated Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like
JPS5742169A (en) * 1980-08-26 1982-03-09 Toshiba Corp Production of semiconductor device
JPS59111370A (ja) * 1982-12-16 1984-06-27 Seiko Instr & Electronics Ltd 不揮発性半導体メモリ
JPS59178773A (ja) * 1983-03-30 1984-10-11 Toshiba Corp 半導体装置の製造方法
US4618876A (en) * 1984-07-23 1986-10-21 Rca Corporation Electrically alterable, nonvolatile floating gate memory device
JPH0722195B2 (ja) * 1985-08-20 1995-03-08 日本電気株式会社 不揮発性半導体記憶装置の製造方法

Also Published As

Publication number Publication date
KR900003875B1 (ko) 1990-06-02
EP0236676A2 (en) 1987-09-16
DE3780484D1 (de) 1992-08-27
US4734887A (en) 1988-03-29
KR870007571A (ko) 1987-08-20
EP0236676A3 (en) 1989-11-02
EP0236676B1 (en) 1992-07-22
JPS62163376A (ja) 1987-07-20
DE3780484T2 (de) 1993-01-21

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