JPH055407B2 - - Google Patents
Info
- Publication number
- JPH055407B2 JPH055407B2 JP62133774A JP13377487A JPH055407B2 JP H055407 B2 JPH055407 B2 JP H055407B2 JP 62133774 A JP62133774 A JP 62133774A JP 13377487 A JP13377487 A JP 13377487A JP H055407 B2 JPH055407 B2 JP H055407B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- buffer circuit
- channel
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00392—Modifications for increasing the reliability for protection by circuit redundancy
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62133774A JPS63299513A (ja) | 1987-05-29 | 1987-05-29 | 出力回路 |
| US07/197,979 US4890016A (en) | 1987-05-29 | 1988-05-24 | Output circuit for CMOS integrated circuit with pre-buffer to reduce distortion of output signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62133774A JPS63299513A (ja) | 1987-05-29 | 1987-05-29 | 出力回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63299513A JPS63299513A (ja) | 1988-12-07 |
| JPH055407B2 true JPH055407B2 (enrdf_load_stackoverflow) | 1993-01-22 |
Family
ID=15112661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62133774A Granted JPS63299513A (ja) | 1987-05-29 | 1987-05-29 | 出力回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4890016A (enrdf_load_stackoverflow) |
| JP (1) | JPS63299513A (enrdf_load_stackoverflow) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01279631A (ja) * | 1988-05-02 | 1989-11-09 | Toshiba Corp | 半導体集積回路の出力回路 |
| US5063308A (en) * | 1988-12-21 | 1991-11-05 | Intel Corporation | Output driver with static and transient parts |
| JPH02218096A (ja) * | 1989-02-17 | 1990-08-30 | Sharp Corp | 半導体メモリの行選択回路 |
| US5036223A (en) * | 1989-05-22 | 1991-07-30 | Kabushiki Kaisha Toshiba | Inverter circuit and chopper type comparator circuit using the same |
| US5045730A (en) * | 1989-12-22 | 1991-09-03 | Gte Laboratories Incorporated | Electrical circuitry providing compatibility between different logic levels |
| JPH03231455A (ja) * | 1990-02-07 | 1991-10-15 | Toshiba Corp | 半導体集積回路 |
| JPH03247117A (ja) * | 1990-02-26 | 1991-11-05 | Nec Corp | Cmos論理回路 |
| US5221910A (en) * | 1990-10-09 | 1993-06-22 | Sgs-Thomson Microelectronics S.A. | Single-pin amplifier in integrated circuit form |
| JP2978302B2 (ja) * | 1991-01-28 | 1999-11-15 | 三菱電機株式会社 | 出力バッファ回路 |
| US5184032A (en) * | 1991-04-25 | 1993-02-02 | Texas Instruments Incorporated | Glitch reduction in integrated circuits, systems and methods |
| US5327021A (en) * | 1991-06-10 | 1994-07-05 | Shinko Electric Ind., Co., Ltd. | Waveform synthesizing circuit |
| US5402356A (en) * | 1992-04-02 | 1995-03-28 | Vlsi Technology, Inc. | Buffer circuit design using back track searching of site trees |
| JP3042567B2 (ja) * | 1992-08-25 | 2000-05-15 | 株式会社高取育英会 | 平均値回路 |
| JPH08307159A (ja) * | 1995-04-27 | 1996-11-22 | Sony Corp | 高周波増幅回路、送信装置、及び受信装置 |
| US5739715A (en) * | 1995-10-31 | 1998-04-14 | Hewlett-Packard Co. | Digital signal driver circuit having a high slew rate |
| JPH10162584A (ja) * | 1996-12-02 | 1998-06-19 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US5949269A (en) * | 1997-01-13 | 1999-09-07 | Intel Corporation | Method and apparatus to reduce signal delay mismatch in a high speed interface |
| JP4300598B2 (ja) * | 1998-06-30 | 2009-07-22 | ソニー株式会社 | 半導体回路の設計方法および製造方法 |
| KR100475046B1 (ko) * | 1998-07-20 | 2005-05-27 | 삼성전자주식회사 | 출력버퍼 및 그의 버퍼링 방법 |
| US6154045A (en) * | 1998-12-22 | 2000-11-28 | Intel Corporation | Method and apparatus for reducing signal transmission delay using skewed gates |
| US6359477B1 (en) * | 1999-06-03 | 2002-03-19 | Texas Instruments Incorporated | Low power driver design |
| US6549036B1 (en) | 2000-05-31 | 2003-04-15 | Micron Technology, Inc. | Simple output buffer drive strength calibration |
| FR2818762B1 (fr) * | 2000-12-22 | 2003-04-04 | St Microelectronics Sa | Regulateur de tension a gain statique en boucle ouverte reduit |
| US6466074B2 (en) * | 2001-03-30 | 2002-10-15 | Intel Corporation | Low skew minimized clock splitter |
| US6870895B2 (en) * | 2002-12-19 | 2005-03-22 | Semiconductor Energy Laboratory Co., Ltd. | Shift register and driving method thereof |
| DE102004054546B4 (de) * | 2004-11-11 | 2011-06-22 | Qimonda AG, 81739 | Treiberschaltung |
| US7982501B2 (en) * | 2005-05-16 | 2011-07-19 | Altera Corporation | Low-power routing multiplexers |
| TWI542141B (zh) * | 2014-08-25 | 2016-07-11 | Univ Nat Chi Nan | RF power amplifier |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3378783A (en) * | 1965-12-13 | 1968-04-16 | Rca Corp | Optimized digital amplifier utilizing insulated-gate field-effect transistors |
| US4065715A (en) * | 1975-12-18 | 1977-12-27 | General Motors Corporation | Pulse duration modulated signal transducer |
| US4103188A (en) * | 1977-08-22 | 1978-07-25 | Rca Corporation | Complementary-symmetry amplifier |
| JPS57180225A (en) * | 1981-04-28 | 1982-11-06 | Fujitsu Ltd | Trigger pulse generating circuit |
| US4782253A (en) * | 1984-02-15 | 1988-11-01 | American Telephone & Telegraph Company, At&T Bell Laboratories | High speed MOS circuits |
| US4786824A (en) * | 1984-05-24 | 1988-11-22 | Kabushiki Kaisha Toshiba | Input signal level detecting circuit |
| US4737670A (en) * | 1984-11-09 | 1988-04-12 | Lsi Logic Corporation | Delay control circuit |
| JP2557619B2 (ja) * | 1985-01-19 | 1996-11-27 | 三洋電機株式会社 | 信号出力回路 |
| JPS62220026A (ja) * | 1986-03-20 | 1987-09-28 | Toshiba Corp | 出力バツフア回路 |
-
1987
- 1987-05-29 JP JP62133774A patent/JPS63299513A/ja active Granted
-
1988
- 1988-05-24 US US07/197,979 patent/US4890016A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4890016A (en) | 1989-12-26 |
| JPS63299513A (ja) | 1988-12-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |