JPH05283467A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

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Publication number
JPH05283467A
JPH05283467A JP4103630A JP10363092A JPH05283467A JP H05283467 A JPH05283467 A JP H05283467A JP 4103630 A JP4103630 A JP 4103630A JP 10363092 A JP10363092 A JP 10363092A JP H05283467 A JPH05283467 A JP H05283467A
Authority
JP
Japan
Prior art keywords
electrode pad
hole
conductive film
film
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4103630A
Other languages
English (en)
Inventor
Toshio Isono
寿男 磯野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4103630A priority Critical patent/JPH05283467A/ja
Priority to US08/035,638 priority patent/US5463255A/en
Publication of JPH05283467A publication Critical patent/JPH05283467A/ja
Pending legal-status Critical Current

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】 【目的】 半導体集積回路の製造方法のスルーホール埋
め込み工程に対応でき、しかもボンディング特性に優れ
た電極パッドを備える半導体集積回路装置を得る。 【構成】 半導体基板１０上に形成される下層の導電膜
（第２アルミニウム膜１３）と、この上に層間絶縁膜
（第２層間絶縁膜１４）を介して形成される上層の導電
膜（第３アルミニウム膜１５）とを微小スルーホール１
４ａで電気接続し、かつこの上層の導電膜１５を下層の
導電膜１３の存在しない平面領域まで延長形成し、この
延長形成した部分をワイヤのボンディング部として電極
パッドを構成する。このため、スルーホール１４ａを集
積回路の内部スルーホールと同様に微小径に形成でき、
スルーホール埋め込み工程に対応させる一方で、電極パ
ッドのボンディング性を改善する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特にワイヤボンディング方式を用いた半導体集積回
路装置に関する。
【０００２】
【従来の技術】半導体チップと外部基板、或いは外部ケ
ースとの接続を行う方法としてワイヤボンディング方式
がある。これは半導体チップ内に設けられた電極パッド
と外部基板、或いは外部ケースの電極部との間を直径が
３０μｍ程度の金線で接続するものであるが、比較的容
易にかつ高信頼度で実現できることから、現在では半導
体集積回路装置の組立の主流となっている。このワイヤ
ボンディング方式では、電極パッドと金線の接合は、先
ずキャピラリと呼ばれる金線の射出口から突出される金
線の先端部に直径８０〜１００μｍ程度の金ボールが形
成されて電極パッドに圧着される。その上で超音波振動
により金ボールと電極パッドとの接合度を増し、密着性
を高めている。このため、電極パッドは、接合面の強度
や接合面の平坦性等に留意する必要がある。
【０００３】図３は従来の電極パッドの構造を示してお
り、（ａ）はレイアウト図、（ｂ）は断面図である。こ
れらの図において、３０は半導体基板、３１は第１アル
ミニウム膜、３２は層間絶縁膜、３３は第２アルミニウ
ム膜、３２ａは前記層間絶縁膜３２に開設されて前記第
１アルミニウム膜３１と第２アルミニウム膜３３を互い
に接続する方形のスルーホールである。このスルーホー
ル３２ａは、一辺の寸法が前述した金ボールの径より大
きい９０〜１１０μｍ程度を有するもので、これによっ
て金ボールと、接合面となる第２アルミニウム膜３３の
強度を高め、更に接合面の平坦性をも確保している。即
ち、仮にスルーホール３２ａの辺寸法が金ボール径より
小さくなると、金ボールとの接合面下に層間絶縁膜３２
が介在されることになり、接合時の圧着力によって層間
絶縁膜３２にクラックを生じる結果となる。クラックは
超音波振動の伝搬を阻害し、更に平坦性をも損なうので
金ボールと電極パッドの密着性は低下する。
【０００４】
【発明が解決しようとする課題】ところで、近年におけ
る半導体製造プロセスのサブミクロン化、及び多層化に
伴い、電極パッドを形成するメタライズ工程に変化が生
じている。つまり、従来のアルミニウムスパッタ工程の
みではサブミクロンオーダに入ったスルーホールを安定
に埋めることが難しくなってきたので、新たにアルミニ
ウムスパッタ工程の前にスルーホール埋め込み工程を設
けるというものである。このスルーホール埋め込み工程
はチップ内の全スルーホールの高さ及び深さが均一でな
いと効果が得られない。スルーホールの高さ、及び深さ
を均一にするには各スルーホールのスルーホール径や直
下のアルミニウムの構造を等しくしたり、周囲のレイア
ウトパターンを一様に揃えることが必要となる。
【０００５】図３の従来の電極パッドにおけるスルーホ
ール３２ａの開口寸法（径）とチップ内部の素子間配線
に用いるスルーホールとではスルーホール径は２桁違
う。更に、周囲のレイアウトパターンにおいても１〜２
μｍ幅の配線アルミニウムが縦横に走る内部領域にある
内部スルーホールと図３のスルーホール３２ａとでは明
らかな差異がある。したがって、図３の従来の電極パッ
ドをスルーホール埋め込み工程のある製造プロセスで形
成すると、スルーホール３２ａの埋め込み不良を起こ
し、電極パッドの平坦性、即ちボンディング特性の点で
問題が生じる。逆に、電極パッドのスルーホールを縮小
すると、所望寸法の電極パッドを得ることは困難にな
る。本発明の目的は、スルーホール埋め込み工程に対応
でき、しかもボンディング特性に優れた電極パッドを備
える半導体集積回路装置を提供することにある。
【０００６】
【課題を解決するための手段】本発明の半導体集積回路
装置は、半導体基板上に形成される下層の導電膜と、こ
の上に層間絶縁膜を介して形成される上層の導電膜とを
微小スルーホールで電気接続し、かつこの上層の導電膜
を前記下層の導電膜の存在しない平面領域まで延長形成
し、この延長形成した部分をワイヤのボンディング部と
して電極パッドを構成する。
【０００７】
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の第１実施例を示しており、（ａ）は
レイアウト図、（ｂ）は断面図である。１０は半導体基
板であり、その上に第１アルミニウム膜１１が通常の配
線幅で形成され、層間絶縁膜１２で被覆される。この層
間絶縁膜１２には微小なスルーホール１２ａが開設さ
れ、この上に第２アルミニウム膜１３が第１アルミニウ
ム膜１１と同じ配線幅で重ねて形成され、前記スルーホ
ール１２ａを介して第１アルミニウム膜１１に接続され
る。更に、この第２アルミニウム膜１３を層間絶縁膜１
４で被覆し、微小なスルーホール１４ａを開設した後、
第３アルミニウム膜１５を形成し、この第３アルミニウ
ム膜１５で電極パッドを形成する。この第３アルミニウ
ム膜１５は前記スルーホール１４ａが存在しない領域に
迄延長形成されて所要の面積寸法の電極パッドとして形
成される。したがって、電極パッドはその一側部におい
てのみスルーホール１４ａによって第２アルミニウム膜
１３に接続される。
【０００８】ここで、前記各スルーホール１２ａ，１４
ａの径は従来の電極パッドにおけるスルーホールよりも
小さくされ、図外の配線層間接続用のスルーホールの径
と同じに形成されている。このため、この実施例では各
アルミニウム膜の相互間での接続抵抗を低減するため
に、複数個のスルーホールを設けている。したがって、
この電極パッドの構造によれば、スルーホール１２ａ，
１４ａの径は他のスルーホールと同じ径寸法になり、近
年におけるスルーホール埋め込み工程に対応でき、その
埋め込み不良は解消される。又、電極パッドのボンディ
ング部は２層分の層間絶縁膜１２，１４が下層に存在し
ているので、金ボール圧着時のクラックが発生し難いも
のとなる。
【０００９】図２は本発明の第２実施例であり、（ａ）
はレイアウト図、（ｂ）は断面図である。この実施例で
は、半導体基板２０上に第１乃至第３のアルミニウム膜
２１，２３，２５を形成し、かつ各アルミニウム膜を第
１乃至第３の層間絶縁膜２２，２４，２６で被覆し、各
アルミニウム膜を微小なスルーホール２２ａ，２４ａに
よって相互に接続する。そして、第３の層間絶縁膜２６
上に微小スルーホール２６ａを開設した上で、第４のア
ルミニウム膜２７を電極パッドとして形成し、スルーホ
ール２６ａにより第３のアルミニウム膜２５に電気接続
している。
【００１０】この構成においても、第４アルミニウム膜
２７で形成される電極パッドの一側部においてのみ微小
スルーホール２２ａ，２４ａ，２６ａによって第１乃至
第４のアルミニウム膜２１，２３，２５，２７が接続さ
れるため、スルーホール径を小さくでき、スルーホール
埋め込み好適におけるスルーホールの埋め込み不良を解
消する。又、電極パッドのボンディング部の下層には３
層分の層間絶縁膜２２，２４，２６が存在しているの
で、金ボール圧着時のクラック発生が防止できる。尚、
図示は省略したが、スルーホールにおける接続抵抗を低
減するために、電極パッドの二辺乃至四辺にわたって複
数個のスルーホールを形成するようにしてもよい。
【００１１】
【発明の効果】以上説明したように本発明は、上層導電
膜の一部において微小スルーホールにより下層導電膜と
の電気接続を行ない、このスルーホールが存在しない上
層導電膜の領域をボンディング部として構成しているの
で、電極パッドを形成するための大開口径のスルーホー
ルを不要とし、スルーホール埋め込み工程を採用する半
導体集積回路製造方法におけるスルーホール埋め込み不
良を解消し、平坦性に優れたボンディング特性の良好な
電極パッドを得ることができる効果がある。
【図面の簡単な説明】
【図１】本発明の第１実施例を示し、（ａ）はレイアウ
ト図、（ｂ）は断面図である。
【図２】本発明の第２実施例を示し、（ａ）はレイアウ
ト図、（ｂ）は断面図である。
【図３】従来の電極パッドを示し、（ａ）はレイアウト
図、（ｂ）は断面図である。
【符号の説明】
１０，２０ 半導体基板 １１，２１ 第１アルミニウム膜 １２，２２ 第１層間絶縁膜 １３，２３ 第２アルミニウム膜 １４，２４ 第２層間絶縁膜 １５，２５ 第３アルミニウム膜 ２６ 第３層間絶縁膜 ２７ 第４アルミニウム膜 １２ａ，１４ａ，２２ａ，２４ａ，２６ａ 微小スルー
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Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 半導体基板上に形成される下層の導電膜
    と、この上に層間絶縁膜を介して形成される上層の導電
    膜とを微小スルーホールで電気接続するとともに、この
    上層の導電膜を前記下層の導電膜の存在しない平面領域
    まで延長形成し、この延長形成した部分をワイヤのボン
    ディング部とした電極パッドを備えることを特徴とする
    半導体集積回路装置。
JP4103630A 1992-03-30 1992-03-30 半導体集積回路装置 Pending JPH05283467A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP4103630A JPH05283467A (ja) 1992-03-30 1992-03-30 半導体集積回路装置
US08/035,638 US5463255A (en) 1992-03-30 1993-03-23 Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4103630A JPH05283467A (ja) 1992-03-30 1992-03-30 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPH05283467A true JPH05283467A (ja) 1993-10-29

Family

ID=14359092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4103630A Pending JPH05283467A (ja) 1992-03-30 1992-03-30 半導体集積回路装置

Country Status (2)

Country Link
US (1) US5463255A (ja)
JP (1) JPH05283467A (ja)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3383081B2 (ja) 1994-07-12 2003-03-04 三菱電機株式会社 陽極接合法を用いて製造した電子部品及び電子部品の製造方法
US5661082A (en) * 1995-01-20 1997-08-26 Motorola, Inc. Process for forming a semiconductor device having a bond pad
JPH08293523A (ja) * 1995-02-21 1996-11-05 Seiko Epson Corp 半導体装置およびその製造方法
US5506450A (en) * 1995-05-04 1996-04-09 Motorola, Inc. Semiconductor device with improved electromigration resistance and method for making the same
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
US6084312A (en) * 1998-10-30 2000-07-04 Samsung Electronics Co., Ltd. Semiconductor devices having double pad structure
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance
US6539372B1 (en) * 1999-11-17 2003-03-25 International Business Machines Corporation Method for providing automated user assistance customized output in the planning, configuration, and management of information systems
US6426284B1 (en) 2000-03-20 2002-07-30 Illinois Tool Works Inc. Method of manufacturing wire bond pad
EP1489659A1 (de) * 2003-06-18 2004-12-22 ABB Technology AG Kontaktmetallisierung für Halbleiterbauelemente
JP2007059867A (ja) * 2005-07-26 2007-03-08 Matsushita Electric Ind Co Ltd 半導体装置
US8089160B2 (en) * 2007-12-12 2012-01-03 International Business Machines Corporation IC interconnect for high current
JP5424747B2 (ja) * 2009-07-06 2014-02-26 ラピスセミコンダクタ株式会社 半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4185294A (en) * 1975-12-10 1980-01-22 Tokyo Shibaura Electric Co., Ltd. Semiconductor device and a method for manufacturing the same
JPS60227444A (ja) * 1984-04-26 1985-11-12 Nec Corp 半導体装置
JPS61187262A (ja) * 1985-02-14 1986-08-20 Matsushita Electronics Corp 半導体素子
JPS61225837A (ja) * 1985-03-29 1986-10-07 Fujitsu Ltd 半導体装置の層間接続方法
JPS61234052A (ja) * 1985-04-10 1986-10-18 Nec Corp 半導体集積回路装置
JPS61292947A (ja) * 1985-06-21 1986-12-23 Hitachi Ltd 半導体装置
JPS6290950A (ja) * 1985-10-16 1987-04-25 Mitsubishi Electric Corp 半導体装置
JPH02123753A (ja) * 1988-11-02 1990-05-11 Fujitsu Ltd 半導体装置及びその製造方法
JP2580301B2 (ja) * 1988-12-27 1997-02-12 株式会社日立製作所 半導体集積回路装置
JP3238395B2 (ja) * 1990-09-28 2001-12-10 株式会社東芝 半導体集積回路

Also Published As

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