JPS61187262A - 半導体素子 - Google Patents

半導体素子

Info

Publication number
JPS61187262A
JPS61187262A JP60026966A JP2696685A JPS61187262A JP S61187262 A JPS61187262 A JP S61187262A JP 60026966 A JP60026966 A JP 60026966A JP 2696685 A JP2696685 A JP 2696685A JP S61187262 A JPS61187262 A JP S61187262A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline silicon
size
film
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60026966A
Other languages
English (en)
Inventor
Koji Nose
幸之 野世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60026966A priority Critical patent/JPS61187262A/ja
Publication of JPS61187262A publication Critical patent/JPS61187262A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01014—Silicon [Si]
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    • H01L2924/01015—Phosphorus [P]
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    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体素子で、特にその電極形状およびその
周辺の構造に関するものである。
従来の技術 半導体素子は、半導体基体面上に能動要素、受動要素等
の回路要素を形成し、アルミニウムもしくはその合金等
の導体層で、各回路要素間接続配線を設ける際に、半導
体素子の外部接続電極であるボンディングパッドを同時
に形成する。ついで、半導体素子表面全体を表面保護を
目的とした絶縁膜で一度覆い、ボンディングパッド上の
絶縁膜の一部を除去して開孔部を設け、導体層の一部を
露出させる。この露出部は後の工程で、この半導体素子
チップを搭載して、その近傍のインナーリードと、金も
しくは、アルミニウムの細線で接続するだめの電極とな
り、導体層とそれを覆う表面保護膜の開孔は、必要に応
じ矩形もしくは多角形をなしていた。
発明が解決しようとする問題点 半導体素子のパッケージ材料は、エポキシ樹脂が多く用
いられる。しかし、樹脂材料を用いたパッケージは、長
時間の高温高湿雰囲気中では、水分が樹脂を通過し、ア
ルミニウム電極の腐食を誘３ペ−ノ 発し、さらに進行すれば半導体素子３と細線との間が断
線し、半導体素子の機能が損われる。
た 本発明は、上記の問題を解決しボンディングパッド構造
である。
問題点を解決するための手段 本発明は、ボンディングパッドの構造を、二層の多結晶
シリコン、一層の層間絶縁膜と一層の電極導体層とで構
成したものである。すなわち、一層目の多結晶シリコン
は、高濃度不純物拡散が施されており内部回路の導体層
との電気的接続とワイヤーボンディングの機械的衝撃に
耐える構造とする。層間絶縁膜は、外部から侵入するイ
オン性の汚染を防止する構造とする。二層目の多結晶シ
リコンは、金属細線による蓋の支持枠となる。そ導 して開孔部中に配置された電極体層は、金属細線と、電
気的に良好な導体である一層目多結晶シリコンとの中間
接続体とする。
作　　用 この構造によると、二層目多結晶シリコンと層間絶縁膜
とに設けた開孔部は、前記電極導体層を金などから成る
ボール部で蓋をして、開孔部内部に同電極導体層を閉じ
込め、外部からの水分の侵入をこの電極部でに、止める
作用をなし、これにより、上記問題点を解決する。
実施例 本発明の実施例を第１図の平面図と、第２図の各工程断
面図を参照して説明する。シリコン基板１上に０．６〜
１．０μｍの熱酸化膜２を形成し、その上に０．３〜１
．０μｍの一層目多結晶シリコン３を積み、高濃度（３
０〜５０Ω／口）に不純物を添加し、表面に形成された
燐ガラスを除去した後ボンディングパッド４位置によ１
３０μｍ口のパターンを形成する。つぎに層間絶縁膜と
しての燐珪酸ガラス５を０．５〜１．０μｍ形成し、そ
の上に０．３〜１．０μｍの二層目多結晶シリコン６を
積み、高濃度（３０〜６０Ω／口）に不純物を添加し、
一層目多結晶シリコン３と向様に表面燐ガラスを除去す
る。そして二層目多結晶シリコン６を、ユ１２０μｍ口
のボンディングパッド４のパターンに形成する。その時
、同時に二層目多結晶シリ５ベージ コンロと層間絶縁燐珪酸ガラス５の両層に６〜５０μｍ
０の開孔７を複数個形成する。更に、アルミニウムやア
ルミニウム合金からなる導体層８を、二層目多結晶シリ
コン６の上に０．５〜１，５７１ｍ蒸着し、−辺の寸法
が開孔７と同じ寸法もしくは＝２μｍ小さい寸法で開孔
７内に設ける。最後に表面保護膜９を所望の厚さに形成
し、ボンディングパッド４の部分の開孔１０を＝１００
μｍＯにあけて完了する。これに金ボール１１でボンデ
ィングを行い導体層８の一部を閉じ込める。
発明の効果 本発明のボンディングパソド構造を採用することで、表
面保護膜の破損、半導体素子の電極部導体層腐食の防止
等の効果が得られる。
【図面の簡単な説明】
第１図は本発明実施例のボンディングパッド部平面図、
第２図は本発明実施例の工程断面図を示す。 １・・・・・シリコン基板、２・・・・・・熱酸化膜、
３・・・・・・−ｉ目多結晶シリコン、４・・・・・・
ボンディングパソ６　＜　・ ド、５・・・・・・層間絶縁燐珪酸ガラス、６・・・・
・・二層目多結晶シリコン、７・・・・・・開孔（二層
目多結晶シリコンと層間絶縁燐珪酸ガラス）８・・・・
・・電極導体層、９・・・・・・表面保護膜、１０・・
・・・・表面保護膜開孔端、１１・・・・・・金ボール
。

Claims (3)

    【特許請求の範囲】
  1. （１）半導体素子のボンディングパッド部に、層間絶縁
    膜を挾んだ二層の多結晶シリコン膜を有し、上層の多結
    晶シリコンと層間絶縁膜との両層に同一寸法の開孔部を
    有し、前記開孔部に位置する下層の多結晶シリコン面上
    に、開孔部寸法より小さい導体層をそなえたことを特徴
    とする半導体素子。
  2. （２）上層多結晶シリコン層間絶縁膜とにあけられた開
    孔部が複数個備えられた特許請求の範囲第１項に記載の
    半導体素子。
  3. （３）下層多結晶シリコンが表面保護膜で覆われた領域
    で内部導体層と接続された特許請求の範囲第１項または
    第２項に記載の半導体素子。
JP60026966A 1985-02-14 1985-02-14 半導体素子 Pending JPS61187262A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60026966A JPS61187262A (ja) 1985-02-14 1985-02-14 半導体素子

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60026966A JPS61187262A (ja) 1985-02-14 1985-02-14 半導体素子

Publications (1)

Publication Number Publication Date
JPS61187262A true JPS61187262A (ja) 1986-08-20

Family

ID=12207895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60026966A Pending JPS61187262A (ja) 1985-02-14 1985-02-14 半導体素子

Country Status (1)

Country Link
JP (1) JPS61187262A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148647A (ja) * 1986-12-12 1988-06-21 Nec Corp 半導体装置
JPH04318944A (ja) * 1991-04-18 1992-11-10 Nec Corp 樹脂封止型半導体装置
US5463255A (en) * 1992-03-30 1995-10-31 Nec Corporation Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion
US6084312A (en) * 1998-10-30 2000-07-04 Samsung Electronics Co., Ltd. Semiconductor devices having double pad structure
US6504252B2 (en) 2000-12-27 2003-01-07 Kabushiki Kaisha Toshiba Semiconductor device with a split pad electrode
CN100431124C (zh) * 2004-09-14 2008-11-05 国际商业机器公司 引线接合焊盘及其制造方法
KR101116313B1 (ko) 2008-01-25 2012-03-14 주식회사 하이닉스반도체 반도체 소자의 본딩 패드부 및 그 형성 방법

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148647A (ja) * 1986-12-12 1988-06-21 Nec Corp 半導体装置
JPH0546980B2 (ja) * 1986-12-12 1993-07-15 Nippon Electric Co
JPH04318944A (ja) * 1991-04-18 1992-11-10 Nec Corp 樹脂封止型半導体装置
US5463255A (en) * 1992-03-30 1995-10-31 Nec Corporation Semiconductor integrated circuit device having an electrode pad including an extended wire bonding portion
US6084312A (en) * 1998-10-30 2000-07-04 Samsung Electronics Co., Ltd. Semiconductor devices having double pad structure
US6504252B2 (en) 2000-12-27 2003-01-07 Kabushiki Kaisha Toshiba Semiconductor device with a split pad electrode
US6670712B2 (en) 2000-12-27 2003-12-30 Kabushiki Kaisha Toshiba Semiconductor device
CN100431124C (zh) * 2004-09-14 2008-11-05 国际商业机器公司 引线接合焊盘及其制造方法
KR101116313B1 (ko) 2008-01-25 2012-03-14 주식회사 하이닉스반도체 반도체 소자의 본딩 패드부 및 그 형성 방법

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