JPH0512867B2 - - Google Patents

Info

Publication number
JPH0512867B2
JPH0512867B2 JP58127055A JP12705583A JPH0512867B2 JP H0512867 B2 JPH0512867 B2 JP H0512867B2 JP 58127055 A JP58127055 A JP 58127055A JP 12705583 A JP12705583 A JP 12705583A JP H0512867 B2 JPH0512867 B2 JP H0512867B2
Authority
JP
Japan
Prior art keywords
insulating layer
layer
silicon
region
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58127055A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59106172A (ja
Inventor
Surikantesuwara Iieru Saburamanian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS59106172A publication Critical patent/JPS59106172A/ja
Publication of JPH0512867B2 publication Critical patent/JPH0512867B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/021Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
JP58127055A 1982-12-07 1983-07-14 電界効果トランジスタの製造方法 Granted JPS59106172A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44754382A 1982-12-07 1982-12-07
US447543 1999-11-23

Publications (2)

Publication Number Publication Date
JPS59106172A JPS59106172A (ja) 1984-06-19
JPH0512867B2 true JPH0512867B2 (enExample) 1993-02-19

Family

ID=23776779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58127055A Granted JPS59106172A (ja) 1982-12-07 1983-07-14 電界効果トランジスタの製造方法

Country Status (3)

Country Link
EP (1) EP0111706B1 (enExample)
JP (1) JPS59106172A (enExample)
DE (1) DE3370247D1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4757361A (en) * 1986-07-23 1988-07-12 International Business Machines Corporation Amorphous thin film transistor device
GB2214349B (en) * 1988-01-19 1991-06-26 Standard Microsyst Smc Process for fabricating mos devices
US4912061A (en) * 1988-04-04 1990-03-27 Digital Equipment Corporation Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
FR2663157B1 (fr) * 1990-06-12 1992-08-07 Thomson Csf Procede d'autoalignement des contacts metalliques sur un dispositif semiconducteur et semiconducteur autoaligne.
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US5439846A (en) * 1993-12-17 1995-08-08 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US5512518A (en) * 1994-06-06 1996-04-30 Motorola, Inc. Method of manufacture of multilayer dielectric on a III-V substrate
US6080672A (en) * 1997-08-20 2000-06-27 Micron Technology, Inc. Self-aligned contact formation for semiconductor devices
KR100236101B1 (ko) * 1997-09-29 1999-12-15 김영환 반도체 소자 및 제조 방법
KR100239422B1 (ko) * 1997-10-28 2000-01-15 김영환 반도체 소자 및 제조 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5928992B2 (ja) * 1975-02-14 1984-07-17 日本電信電話株式会社 Mosトランジスタおよびその製造方法
US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
FR2481005A1 (fr) * 1980-04-17 1981-10-23 Western Electric Co Procede de fabrication de transistors a effet de champ a canal court
US4330931A (en) * 1981-02-03 1982-05-25 Intel Corporation Process for forming metal plated regions and lines in MOS circuits

Also Published As

Publication number Publication date
DE3370247D1 (en) 1987-04-16
EP0111706B1 (en) 1987-03-11
EP0111706A1 (en) 1984-06-27
JPS59106172A (ja) 1984-06-19

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